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z80 cpu peripherals user manual um008101-0601 disclaimer ii this publication is subject to replacement by a later edition. to determine whether a later edition exists, or to request copies of publications, contact: zilog worldwide headquarters 910 e. hamilton avenue campbell, ca 95008 telephone: 408.558.8500 fax: 408.558.8300 www.zilog.com windows is a registered trademark of microsoft corporation. document disclaimer ?2001 by zilog, inc. all rights reserved. information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not assume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. devices sold by zilog, inc. are covered by warranty and limitation of liability provisions appearing in the zilog, inc. terms and conditions of sale. zilog, inc. makes no warranty of merchantability or fitness for any purpose except with the express written approval of zilog, use of information, devices, or technology as critical components of life support systems is not authorized. no licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
z80 cpu peripherals user manual um008101-0601 table of contents iii table of contents counter/timer channels ctcfeatures ............................................1 ctcgeneraldescription ................................1 ctcarchitecture .........................................2 overview.............................................2 structureofchannellogic...............................3 interruptcontrollogic ..................................7 ctcpindescription.......................................9 pinfunctions .........................................9 ctcoperatingmodes ....................................16 overview............................................16 ctc counter mode ...................................16 ctctimermode .....................................17 ctc programming .......................................18 overview............................................18 loadingthechannelcontrolregister ....................19 loadingthetimeconstantregister......................22 loadingtheinterruptvectorregister.....................22 ctc timing ............................................24 overview............................................24 ctcwritecycle .....................................24 ctcreadcycle ......................................25 ctccountingandtiming ..............................26 ctcinterruptservicing ...................................27 overview............................................27 interrupt acknowledge cycle ............................28 returnfrominterruptcycle .............................29 daisy-chaininterruptservicing ..........................30
z80 cpu peripherals user manual um008101-0601 table of contents iv direct memory access dmaoverview .........................................33 cpudatatransfers ...................................33 dmadatatransfers ..................................35 dmacharacteristics ..................................37 dmafunctionaldescription ...............................43 features .............................................43 overview............................................44 programming ........................................45 classesofoperation ...................................46 modesofoperation ...................................49 transferspeed .......................................56 addressgeneration....................................57 bytematching(searching)..............................58 interrupts ............................................59 autorestart .........................................60 pulsegeneration ......................................60 variablecycle .......................................60 eventsandactions ....................................61 pindescription ..........................................62 internalstructure ........................................71 generalorganization ..................................71 controlandstatusregisters ............................72 addressandbytecounting .............................75 buscontrol ..........................................77 interrupts ............................................79 programming ...........................................89 overview............................................89 writeregisters .......................................91 writeregister0group.................................92 writeregister1group.................................95 writeregister2group.................................97
z80 cpu peripherals user manual table of contents um008101-0601 v direct memory access (continued) writeregister3group.................................97 writeregister4group.................................99 writeregister5group................................102 writeregister6group................................104 readregisters ......................................113 reviewofprogrammingsequences ......................117 applications ...........................................128 z80dmaandcpu ..................................128 z80dmaandz80sioexample........................138 usingthez80dmawithotherprocessors...............142 performancelimitations..................................148 buscontention ......................................148 controloverhead ....................................149 timing................................................150 thecpuasbusmaster...............................150 thedmaasbusmaster ..............................152 registerbitfunctions ...................................170 writeregisterbitfunctions ...........................170 readregisterbitfunctions ............................174 parallel input/output overview..............................................175 features ...............................................175 pioarchitecture ........................................176 overview...........................................176 pindescription .........................................180 programmingthepio ....................................187 reset ..............................................187 loadingtheinterruptvector ...........................188 selectinganoperatingmode ..........................189 setting the interrupt control word ......................191
z80 cpu peripherals user manual um008101-0601 table of contents vi parallel input/output (continued) timing................................................192 outputmode(mode0) ................................192 input mode (mode 1) .................................193 bidirectionalmode(mode2) ...........................194 controlmode(mode3) ...............................195 interruptservicing ......................................197 applications ...........................................199 extendingtheinterruptdaisy-chain.....................199 i/odeviceinterface ..................................200 controlinterface .....................................202 programming summary ..................................205 overview...........................................205 loadinterruptvector .................................205 setmode ...........................................205 setinterruptcontrol ..................................206 serial input/output overview..............................................207 features ...............................................207 pindescription .........................................210 pinfunctions .......................................210 bonding options .....................................213 architecture ...........................................222 overview...........................................222 datapath...........................................223 functionaldescription ................................226 asynchronous operation .................................230 overview...........................................230 asynchronous transmit ...............................232 asynchronous receive ................................235 synchronous operation ...................................238 overview...........................................238
z80 cpu peripherals user manual table of contents um008101-0601 vii synchronous modes of operation .......................240 serial input/output (continued) synchronous transmit ................................244 synchronous receive .................................249 sdlc(hdlc)operation.................................255 overview...........................................255 sdlctransmit......................................256 sdlc receive ......................................265 programming ..........................................272 overview...........................................272 writeregisters ......................................272 readregisters ......................................292 applications ...........................................301 overview...........................................301 timing................................................305 readcycle .........................................305 writecycle .........................................305 interrupt acknowledge cycle ...........................306 returnfrominterruptcycle............................307 daisychaininterruptnesting ..........................308
z80 cpu peripherals user manual um008101-0601 table of contents viii
z80 cpu peripherals user manual list of figures um008101-0601 ix list of figures counter/timer channels figure1. ctcblockdiagram ...............................3 figure2. channelblockdiagram ............................4 figure3. z8016-bitpointer(interruptstartingaddress) ..........8 figure4. ctcpinconfiguration ............................10 figure5. packageconfiguration ............................10 figure6. 44-pinchipcarrierpinassignments .................11 figure7. 44-pinquadflatpackpinassignments ..............12 figure8. mode2interruptoperation ........................23 figure9. ctcwritecycle ................................25 figure10. ctcreadcycle .................................26 figure 11. ctc counting and timing .........................27 figure 12. interrupt acknowledge cycle .......................29 figure13. returnfrominterruptcycle ........................30 figure14. daisy-chaininterruptservicing .....................31 direct memory access figure15. typicalcpui/osequence .........................34 figure 16. conceptual comparison of various i/o transfer methods 39 figure17. modesofoperation ..............................42 figure18. classofoperation................................47 figure19. basicfunctionsofthez80dma ....................49 figure20. transfer/searchonebyte ..........................51 figure21. bytemode......................................52 figure22. burstmode .....................................53 figure 23. continuous mode ................................55
z80 cpu peripherals user manual um008101-0601 list of figures x direct memory access (continued) figure24. variablecyclelength............................ 61 figure25. pinfunctions(cmosplccpackageonly) .......... 67 figure26. 40-pindippinassignments ....................... 68 figure 27. 44-pin plcc pin assignments (z8410 nmos) ........ 69 figure 28. 44-pin plcc pin assignments (z84c10 nmos) . . . . . . 70 figure29. z80dmablockdiagram ......................... 71 figure 30. write register organization (left) and read register organi- zation(right) ................................... 74 figure31. bus-requestingdaisy-chain ...................... 79 figure32. z80interruptsequence ........................... 81 figure33. interruptserviceroutine.......................... 83 figure34. interruptpending(ip)latch ....................... 84 figure35. interruptunderservice(ius)latch ................. 84 figure36. interruptonready(ior)latch .................... 86 figure37. interruptdaisy-chain ............................ 88 figure38. pollingforaservicerequestbit ................... 89 figure 39. write-register pointing methods ................... 92 figure40. writeregister0group ........................... 94 figure41. writeregister1group ........................... 96 figure42. writeregister2group ........................... 97 figure43. writeregister3group ........................... 99 figure44. writeregister4group .......................... 102 figure45. writeregister5group .......................... 104 figure46. writeregister6group .......................... 107 figure 47. read register 0 through read register 6 . ........... 116 figure48. z80/z8000clockdriver ......................... 129 figure49. chipenabledecodingwithz80cpu .............. 131
z80 cpu peripherals user manual list of figures um008101-0601 xi direct memory access (continued) figure50. ce/waitmultiplexer ...........................133 figure51. simultaneoustransfermultiplexer .................133 figure52. simultaneoustransfer ...........................134 figure53. delayingtheleadingedgeofmwr ................135 figure54. databusbuffercontrolexample ..................138 figure55. dma-sioenvironment ..........................142 figure 56. connecting dma to demultiplexed address/data buses 145 figure 57. z8000/z80 peripheral interface ....................147 figure58. dmabus-mastergate(byteorburstmodesonly) ....149 figure59. cpu-to-dmawritecyclerequirements ............151 figure60. cpu-to-dmareadcyclerequirements .............152 figure 61. sequential memory-to-i/o transfer, standard timing (searchingisoptional) ...........................154 figure 62. sequential i/o-to-memory transfer, standard timing (searchingisoptional) ...........................155 figure 63. simultaneous memory-to-i/o transfer (burst and continuous mode) ........................................156 figure64. simultaneousmemory-to-i/otransfer(bytemode)....157 figure65. busrequestandacceptancetiming ................159 figure66. busreleaseinbytemode ........................160 figure 67. bus release on end-of-block (burst and continuous modes) ..............................160 figure 68. bus release on match (burst and continuous modes) . .161 figure69. busreleaseonnotready(burstmode) .............162 figure70. rdylineinbytemode ..........................163 figure71. rdylineinburstmode .........................164 figure 72. rdy line in continuous mode ....................165 figure73. variable-cycleandedgetiming ...................166
z80 cpu peripherals user manual um008101-0601 list of figures xii direct memory access (continued) figure74. waitlinesamplinginvariable-cycletiming ...... 167 figure 75. interrupt acknowledge .......................... 169 figure76. writeregister0group .......................... 170 figure77. writeregister1group .......................... 170 figure78. writeregister2group .......................... 171 figure79. writeregister3group .......................... 171 figure80. writeregister4group .......................... 172 figure81. writeregister5group .......................... 173 figure82. writeregister6group .......................... 173 figure83. readregister0through6bitfunctions............. 174 parallel input/output figure84. pioblockdiagram ............................. 177 figure85. porti/oblockdiagram.......................... 178 figure86. piopinfunctions .............................. 184 figure87. 44-pinplccpinassignments .................... 185 figure88. 44-pinqfppinassignments ..................... 186 figure89. 40-pindippinassignments ...................... 187 figure90. mode0(output)timing ......................... 193 figure 91. mode 1 (input) timing .......................... 194 figure92. porta,mode2(bidirectional)timing .............. 195 figure93. controlmode(mode3)timing ................... 196 figure 94. interrupt acknowledge timing .................... 198 figure95. returnfrominterruptcycle ...................... 198 figure96. daisy-chaininterruptservicing ................... 199 figure 97. a method of extending the interrupt priority daisy-chain ................................... 200
z80 cpu peripherals user manual list of figures um008101-0601 xiii parallel input/output (continued) figure98. exampleofi/ointerface..........................201 figure99. controlmodeapplication ........................204 serial input/output figure 100. z80 sio block diagram . . ........................209 figure 101. z80 sio/0 functions .............................214 figure 102. z80 zio/0 pin assignments .......................215 figure 103. z80 sio/1 pin functions . . ........................216 figure 104. z80 zio/1 pin assignments .......................217 figure 105. z80 sio/2 pin functions . . ........................218 figure 106. z80 zio/2 pin assignments .......................219 figure 107. z80 sio/3 pin assignments .......................220 figure 108. z80 sio/4 pin assignments .......................221 figure 109. transmit and receive data path ....................226 figure 110. interrupt structure ...............................230 figure 111. asynchronous message format ....................231 figure 112. synchronous formats ............................239 figure 113. transmit/receive sdlc/hdlc message format ......256 figure 114. write register 0 ................................274 figure 115. write register 1 ................................279 figure 116. write register 2 ................................282 figure 117. write register 3 ................................284 figure 118. write register 4 ................................286 figure 119. write register 5 ................................289 figure 120. write register 6 ................................290 figure 121. write register 7 ................................291 figure 122. read register 0 .................................294 figure 123. read register 1 .................................299
z80 cpu peripherals user manual um008101-0601 list of figures xiv serial input/output (continued) figure 124. read register 2 (channel b only) ................. 301 figure 125. synchronous/asynchronous processor-to-processor commu- nication(directwiretoremotelocations) .......... 302 figure 126. synchronous/asynchronous processor-to-processor communication (using telephone line) . ........... 302 figure 127. data concentrator . ............................. 304 figure 128. read cycle timing ............................. 305 figure 129. write cycle timing ............................. 306 figure 130. interrupt acknowledge cycle timing ............... 307 figure 131. return from interrupt cycle timing ................ 308 figure 132. typical interrupt service ......................... 309
z80 cpu peripherals user manual list of tables um008101-0601 xv list of tables counter/timer channels table1. channelvalues ...................................4 table2. channelcontrolregister ...........................5 table3. interruptvectorregister ...........................7 table4. channelselecttruthtable.........................13 table5. channelcontrolregister ..........................19 table6. timeconstantregister............................22 table7. interruptvectorregister ..........................23 direct memory access table 8. maximum transfer and search speeds (burst and continuous modes) ........................................57 table 9. reduction in z80 cpu throughput per kbaud (bytemodetransfers) ............................57 table10. eventsandactions ...............................62 table 11. contents of counters after dma stops because of end-of- block(transferoperations) ........................76 table 12. contents of counters after dma stops due to byte match (searchortransfer/searchoperations) ...............76 table13. dmastatus.....................................90 table14. reinitializestatusbyte ...........................110 table15. controlbyteorder ..............................118 table16. sampledmaprogram ...........................126 table17. receiveeventsequence ..........................139 table18. transmiteventsequence .........................139
z80 cpu peripherals user manual um008101-0601 list of tables xvi parallel input/output table19. piomodeselection............................. 189 serial input/output table20. writeregisterfunctions ......................... 223 table21. readregisterfunctions ......................... 223 table 22. contents of write registers 3, 4, and 5 in asynchronous modes ....................................... 232 table 23. asynchronous mode ............................ 233 table 24. contents of write registers 3, 4, and 6 in synchronous modes ............................ 241 table25. bisynctransmitmode .......................... 242 table26. bisyncreceivemode ........................... 252 table 27. contents of write registers 3, 4, and 5 in sdlc modes 258 table28. sdlctransmitmode ........................... 262 table29. sdlcreceivemode............................ 268 table30. channelselectfunctions ........................ 272 table31. writeregister0................................ 273 table32. z80siocommands ............................ 275 table33. writeregister1................................ 277 table34. resetcommands ............................... 277 table35. vectorresults ................................. 278 table36. receiveinterruptmodes ......................... 279 table37. wait/readyfunctions ........................... 280 table38. writeregister2interruptvector .................. 281 table39. writeregister3logiccontrol .................... 282 table40. serialbits/character ............................ 284 table41. writeregister4rxandtxcontrol ................ 285 table42. stopbits ..................................... 285
z80 cpu peripherals user manual list of tables um008101-0601 xvii serial input/output (continued) table43. syncmodes....................................286 table44. clockrate.....................................287 table45. writeregister5transmittercontrol ................287 table46. transmitbits...................................289 table47. datacharacterformat ...........................290 table48. writeregister6transmitsync ....................291 table49. writeregister7receivesync .....................291 table50. readregister0rxandtxbuffers .................292 table 51. read register 1 special receive condition status ......297 table52. residuecodes..................................297 table53. receivecharacterlength .........................298 table54. interruptvector.................................300
z80 cpu peripherals user manual um008101-0601 list of tables xviii

um008101-0601 counter/timer channels counter/timer channels ctc features ? four independently programmable counter/timer channels (ctc), each with a readable down-counter and a selectable 16 or 256 prescaler. down-counters are reloaded automatically at zero count selectable positive or negative trigger initiates timer operation three channels have zero count/timeout outputs capable of driving darlington transistors nmos version for high-cost performance solutions cmos version for the designs requiring low power consumption nmos z0843004 - 4 mhz, z0843006 - 6.17 mhz cmos z84c3006 - dc to 6.17 mhz, z84c3008 dc to 8 mhz, z84c3010 - dc to 10 mhz interfaces directly to the z80 cpu. interfaces to the z80 sio for baud rate generation standard z80 family daisy-chain interrupt structure provides fully vectored, prioritized interrupts without external logic. the ctc may also be used as an interrupt controller a 6 mhz version supports 6.144 mhz cpu clock operation ctc general description the z80 ctc is a four-channel counter/timer that can be programmed by system software for a broad range of counting and timing applications. these four independently programmable channels satisfy common

um008101-0601 counter/timer channels microcomputer system requirements for event counting, interrupt and interval timing, and general clock rate generation. system design is simplified by connecting the ctc directly to both the z80 cpu and the z80 sio with no additional logic. in larger systems, address decoders and buffers may be required. the ctc allows easy programming: each channel is programmed with two bytes; a third is necessary when interrupts are enabled. when started, the ctc counts down, automatically reloads its lime constant, and resumes counting. software timing loops are eliminated. interrupt processing is simplified because only one vector needs to be specified; the ctc internally generates a unique vector for each channel. the z80 ctc requires a single +5v power supply and the standard z80 single-phase system clock. it is packaged in 28-pin dips, a 44-pin plastic chip carrier, and a 44-pin quad flat pack. the qfp package is only available for cmos versions. ctc architecture overview the internal structure of the z80 ctc consists of: a z80 cpu bus interface, internal control logic four sets of counter/timer channel logic interrupt control logic the four independent, counter/timer channels are identified by sequential numbers from 0 to 3. the ctc can generate a unique interrupt vector for each separate channel for automatic vectoring to an interrupt service routine. the four channels can be connected in four contiguous slots in the standard z80 priority chain with channel number 0 having the highest

um008101-0601 counter/timer channels priority. the cpu bus interface logic allows the ctc device to interface directly to the cpu with no other external logic. however, port address decoders and/or line buffers may be required for large systems. a block diagram of the z80 ctc is depicted in figure 1. figure 1. ctc block diagram structure of channel logic the structure of one of the four sets of counter/timer channel logic is illustrated in figure 2. this logic is composed of: two registers two counters control logic the registers consist of an 8-bit time constant register and an 8-bit channel control register. the counters consist of an 8-bit cpu-readable down-counter and an 8-bit prescaler. from z80 cpu data control 8 6 cpu bus i/o internal control logic interrupt logic counter/ timer logic reset zc/to 3 4 ieo int iei internal bus

um008101-0601 counter/timer channels in channel control register and logic the channel control register (8-bit) and logic is written to by the cpu to select the modes and parameters of the channel. within the ctc device, four such registers correspond to the four counter/timer channels. the register to be written to is determined by the encoding of two channel select input pins: cs0 and cs1, which are usually attached to a0 and a1 of the cpu address bus. the channel values are described in table 1. in the control word, which is written to program each channel control register, bit 0 is always set; the other seven bits are programmed to select alternatives on the channel?s operating modes and parameters. these values are described in table 2. for a more complete discussion, see ?ctc operating modes? on page 16 and ?ctc programming? on page 18). figure 2. channel block diagram table 1. channel values cs0 cs1 channel 0 0 0 channel 1 0 1 channel 2 1 0 channel 3 1 1 zc/to prescaler clk clk/trg internal bus 8-bit down counter time constant register channel control logic

um008101-0601 counter/timer channels the prescaler the prescaler is an 8-bit device that is used in the timer mode only. the prescaler is programmed by the cpu through the channel control register to divide its input, the system clock (0), by 16 or 256. the output of the prescaler is then fed as an input to clock the down-counter. each time that table 2. channel control register 76543210 interrupt mode prescaler val ue * clk/trg section time trigger* time constant reset control or vec to r r/w r/w r/w r/w r/w r/w r/w r/w bit number field r/w value description 7 interrupt r/w 1 0 enable interrupt disable interrupt 6mode r/w1 0 counter mode timer mode 5 prescaler value* r/w 1 0 256 16 4 clk/trg edge section r/w 1 0 rising edge falling edge 3 time trigger* r/w 1 0 clk/trg pulse starts timer automatic trigger when time constant is loaded 2 time constant r/w 1 0 time constant follows no time constant follows 1 reset r/w 1 0 software reset continue operation 0 control or vector r/w 1 0 control vec to r *timer mode only

um008101-0601 counter/timer channels the down-counter counts to zero, the down-counter is automatically reloaded with the contents of the time constant register. this process divides the system clock by an additional factor of the time constant. each time the down-counter counts to zero, its output, zero count/timeout (zc/ to), is pulsed high. the time constant register the 8-bit time constant register is used in both counter and timer modes. it is programmed by the cpu just after the channel control word, with an integer time constant value of 1 through 256. this register loads the programmed value to the down-counter when the ctc is first initialized and reloads the same value into the down-counter automatically whenever it counts down thereafter to zero. if a new time constant is loaded into the time constant register while a channel is counting or timing, the present down count is completed before the new time constant is loaded into the down counter. for details about writing a time constant to a ctc channel, see ?ctc programming? on page 18 the down-counter the down-counter is an 8-bit register that is used in both counter and timer modes. this register is loaded by the time constant register both initially, and when it counts down to zero. in the counter mode, the down-counter is decremented by each external clock edge. in the timer mode, it is decremented by the clock output of the prescaler. by performing a simple i/o read at the port address assigned to the selected ctc channel, the cpu can access the contents of the down-counter and obtain the number of counts-to-zero. any of the four ctc channels may be programmed to generate an interrupt request sequence each time the zero count is reached. in channels 0, 1, and 2, a signal pulse appears at the corresponding zc/to pin when the zero count condition is reached. because of package pin limitations, however, channel 3 does not have this pin and so may be used only in applications where this output pulse is not required.

um008101-0601 counter/timer channels interrupt control logic the interrupt control logic insures that the ctc acts in accordance with z80 system interrupt protocol for nested priority interrupting and return from interrupt. the priority of any system device is determined by its physical location in a daisy-chain configuration. two signal lines, ciei and ieo, are provided in ctc devices to form this system daisy-chain. the device closest to the cpu has the highest priority. within the ctc, interrupt priority is predetermined by channel number, with channel 0 having highest and channel 3 the lowest priority. see table 3. the purpose of a ctc-generated interrupt, as with any peripheral device, is to force the cpu to execute an interrupt service routine. according to z80 system interrupt protocol, lower priority devices or channels may not interrupt higher priority devices or channels that have not had their interrupt service routines completed. however, high priority devices or channels may interrupt the servicing of lower priority devices or channels. table 3. interrupt vector register 76543210 supplied by user channel identifier word r/w r/w r/w bit number field r/w value description 7?3 reserved r/w supplied by user 2?1 channel identifier (automatically inserted by ctc) r/w 11 10 01 00 channel 3 channel 2 channel 1 channel 0 0word r/w1 0 control interrupt vector

um008101-0601 counter/timer channels a ctc channel may be programmed to request an interrupt every time its down-counter reaches a count of zero. however, using this feature requires that the cpu be in interrupt mode 2. after the interrupt request, the cpu sends out an interrupt acknowledge. the ctc?s interrupt control logic determines the highest-priority channel requesting an interrupt. if the ctc?s iei input is active, indicating that it has priority within the system daisy-chain, it places an 8-bit interrupt vector on the system data bus as follows: 1. the high order five bits of this vector were written to the ctc earlier as part of the ctc initial programming process. 2. the next two bits are provided by the ctc?s interrupt control logic as a binary code corresponding to the highest-priority channel requesting an interrupt. 3. the low-order bit of the vector is always zero according to a convention (figure 3). this interrupt vector is used to form a pointer to a location in memory where the address of the interrupt service routine is stored in a table. the vector represents the least-significant eight bits. the cpu reads the contents of the i register to provide the most-significant eight bits of the 16-bit pointer. the address pointed to in memory contains the low-order byte and the next highest address contains the high-order byte of an address, which in turn contains the first op code of the interrupt service routine. thus, in mode 2, a single 8-bit vector stored in an interrupting ctc can result in an indirect call to any memory location (figure 3). figure 3. z80 16-bit pointer (interrupt starting address) 0 vector 7bitsfrom peripheral 1reg contents z80 16-bit pointer (interrupt starting address)

um008101-0601 counter/timer channels according to z80 system convention, all addresses in the interrupt service routine table place their low-order byte in an even location in memory, and their high-order byte in the next highest location in memory. this location is always odd so that the least-significant bit of any interrupt vector is always even. therefore, the least-significant bit of any interrupt vector always zero. the reti instruction is used at the end of an interrupt service routine to initialize the daisy chain enable line ieo for control of nested priority interrupt handling. the ctc monitors the system data bus and decodes this instruction when it occurs. therefore, the ctc channel control logic knows when the cpu has completed servicing an interrupt. ctc pin description pin functions diagrams of the z80 ctc pin configuration and z80 ctc package configuration are illustrated in figure 4 through figure 7, respectively. this section describes the function of each pin.

um008101-0601 counter/timer channels figure 4. ctc pin configuration figure 5. package configuration daisy-chain interrupt control ctc control from cpu cpu data bus z80 ctc channel signals clk +5v gnd clk/trg0 zc/to0 clk/trg1 zc/to1 clk/trg2 zc/to2 clk/trg3 reset int ieo iei rd iorq m1 cs1 cs0 ce d0 d0 d1 d2 d3 d4 d5 d6 d7 d4 d5 d6 d7 gnd rd zc/to0 zc/to1 izc/to2 iorq ieo int iei m1 1 2 3 4 6 7 8 9 10 5 11 12 13 14 d3 d2 d1 d0 +5v clk/trg1 clk/trg2 clk/trg3 cs1 cs0 reset ce clk z80 ctc 28 27 26 25 23 22 21 20 19 24 18 17 16 15 clk/trg0

um008101-0601 counter/timer channels figure 6. 44-pin chip carrier pin assignments 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 n/c n/c +5v n/c n/c n/c cs1 clk/trg3 clk/trg0 clk/trg1 clk/trg2 z80 ctc 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 n/c d7 d6 n/c d5 d4 d3 d2 d1 d0 n/c n/c int n/c iei m1 n/c reset cs0 n/c ce clk gnd n/c rd zc/to0 n/c zc/to1 zc/to2 iorq n/c ieo n/c

um008101-0601 counter/timer channels figure 7. 44-pin quad flat pack pin assignments bit 7?bit 0 system data bus (bidirectional, tristate). thisbusisusedtotransferall date and command words between the z80 cpu and the z80 ctc. there are eight bits on this bus, of which bit 0 is the least-significant. csi cso channel select (input, active high). these pins form a 2-bit binary address code for selecting one of the four independent ctc channels for an i/o writeorread.(seetable4). 34 33 n/c cs1 clk/trg3 clk/trg2 n/c n/c clk/trg1 clk/trg0 n/c +5v n/c ieo iorq n/c zc/to2 zc/to1 n/c zc/to0 n/c rd gnd d7 cs0 rese t ce n/c clk n/c m1 n/c iei n/c int d0 d1 d2 d3 n/c n/c n/c d4 d5 d6 n/c 44 22 12 11 1 cmos z80 ctc

um008101-0601 counter/timer channels ce chip enable (input, active low). a low level on this pin enables the ctc to accept control words, interrupt vectors, or time constant data words from the z80 data bus during an i/o write cycle; or to transmit the contents or the down-counter to the cpu during an i/o read cycle. in most applications this signal is decoded from the eight least-significant bits of the address bus for any of the four i/o port addresses that are mapped to the four counter/timer channels. clock( ) system clock (input). this single-phase clock is used by the ctc to internally synchronize certain signals. m1 machine cycle one signal from cpu (input, active low). when m1 is activeandtherd signal is active, the cpu fetches an instruction from memory. when m1 is active and the iorq signal is active, the cpu acknowledges an interrupt, alerting the ctc to place an interrupt vector on the z80 data bus if it has daisy-chain priority and one of its channels has requested an interrupt. table 4. channel select truth table cs1 cs0 channel 0 0 0 channel l 0 1 channel 2 1 0 channel 3 1 1

um008101-0601 counter/timer channels iorq input/output request from cpu (input, active low). the iorq signal is used in conjunction with the ce and rd signals to transfer data and channel control words between the z80 cpu and the ctc. during a ctc write cycle, iorq and ce must be true and rd false. the ctc does not receive a specific write signal. instead it generates one internally from the inverse of a valid rd signal. in a ctc read cycle, iorq ,ce ,andrd must be active to place the contents of the down-counter on the z80 data bus. if iorq and m1 are both true, the cpu is acknowledging an interrupt request, and the highest priority interrupting channel places its interrupt vector on the z80 data bus. rd read cycle status from the cpu (input, active low). the rd signal is used in conjunction with the iorq and ce signals to transfer data and channel control words between the z80 cpu and the ctc. during a ctc write cycle, iorq and ce must be true and rd false. the ctc does not receive a specific write signal, instead it generates one internally from the inverse of a valid rd signal. in a ctc read cycle, iorq ce ,andrd must be active to place the contents of the down-counter on the z80 data bus. iei interrupt enable in (input, active high). this signal is used to form a system-wide interrupt daisy-chain which establishes priorities when more than one peripheral device in the system has interrupting capability. a high level on this pin indicates that no other interrupting devices of higher priority in the daisy chain are being serviced by the z80 cpu. ieo interrupt enable out (output, active high. the ieo signal, in conjunction with iei, is used to form a system-wide interrupt priority daisy-chain. ieo is high only if iei is high and the cpu is not servicing

um008101-0601 counter/timer channels an interrupt from any ctc channel. therefore, this signal blocks lower- priority devices from interrupting while a higher-priority interrupting device is being serviced by the cpu. int interrupt request (output, open-drain, active low). this signal goes true when a ctc channel, which has been programmed to enable interrupts, has a zero-count condition in its down-counter. reset reset (input, active low) . this signal stops all channels from counting and resets interrupt enable bits in all control registers, thereby disabling ctc-generated interrupts. the zc/to and int outputs go inactive, ieo reflects iei, and the ctc?s data bus output drivers go to the high- impedance state. clk/trg3?clk/trg0 external clock/timer trigger (input, user-selectable active high or low). four clk/trg pins correspond to the four independent ctc channels. in the counter mode, every active edge on this pin decrements the down-counter. in the timer mode, an active edge on this pin initiates the timing function. the user may select the active edge to be either rising or falling. zc/to2-ac/to0 zero count/timeout (output, active high). three zc/to pins correspond to ctc channels 2 through 0. (because of package pin limitations channel 3 has no zc/to pin.) in either counter mode or timer mode, when the down-counter decrements to zero, an active high pulse appears at this pin.

um008101-0601 counter/timer channels ctc operating modes overview at power-on, the z80 ctc state is undefined. asserting reset puts the ctc in a known state. before a channel can begin counting or timing, a channel control word and a time constant data word must be written to the appropriate registers of that channel. additionally, if a channel has been programmed to enable interrupts, an interrupt vector word must be written to the ctc?s interrupt control logic. (for further details, refer the ?ctc programming? on page 18) when the cpu has written all of these words to the ctc, all active channels are programmed for immediate operation in either the counter mode or the timer mode. ctc counter mode in ctc counter mode, the ctc counts edges of the clk/trg input. this mode is programmed for a channel when its channel control word is written with bit 6 set. the channel?s external clock (clk/trg) input is monitored for a series of triggering edges. after each, in synchronization with the next rising edge of (the system clock), the down-counter (which is initialized with the time constant data word at the start of each sequence of down-counting) is decremented. although there is no setup time requirement between the triggering edge of the external clock and the rising edge of (clock), the down-counter is not decremented until the following pulse. a channel?s external clock input is pre programmed by bit 4 of the channel control word to trigger the decrementing sequence with either a high- or a low-going edge. in channels 0, 1, or 2, when the down-counter is successively decremented from the original time constant (until it reaches zero), the zero count (zc/ to) output pin for that channel is pulsed active (high). due to package pin limitations, this pin does not exist on channel 3 and so this pin may only be

um008101-0601 counter/timer channels used in applications where this output pulse is not required. additionally, if the channel is pre-programmed by bit 7 of the channel control word, an interrupt request sequence is generated. for more details, see the ctc interrupt servicing section the zero-count condition also results in the automatic reload of the down- counter with the original time constant data word in the time constant register. there is no interruption in the sequence of continued down- counting. if the time constant register is written with a new time constant data word while the down-counter is decrementing, the present count is completed before the new time constant is loaded into the down-counter. ctc timer mode in ctc timer mode, the ctc generates timing intervals that are an integer value of the system clock period. this mode is programmed for a channel when its channel control word is written with bit 6 reset. the channel then may be used to measure intervals of time based on the system clock period. the system clock is fed through the prescaler and the down- counter. depending on the pre programmed bit 5 in the channel control word, the prescaler divides the system clock by a factor of 16 or 256. the output of the prescaler is then used as a clock to decrement the down- counter, which may be pre programmed with any time constant integer between 1 and 256. the time constant is automatically reloaded into the down-counter at each zero-counter condition. at zero count, the channel?s time cut (zc/to) output (which is the output of the down-counter) is pulsed, resulting in a uniform pulse train of the precise period given by the product as shown below. where t c is the system clock, p is the prescaler factor of 16 or 256, and tc is the pre-programmed time constant.

um008101-0601 counter/timer channels timing may be initialized automatically or with a triggering edge at the channel?s timer trigger (clk/trg) input. this timing is determined by programming bit 3 of the channel control word. if bit 3 is reset?, the timer automatically begins operation at the start of the cpu cycle following the i/ o write machine cycle that loads the time constant data word to the channel. if bit 3 is set, the timer begins operation on the second succeeding rising edge of after the timer trigger edge following the loading of the time constant data word. if no time constant word is to follow, the timer begins operation on the second succeeding rising edge of after the timer trigger edge and following the control word write cycle. bit 4 of the channel control word is pre programmed to select whether the timer trigger is sensitive to a rising or falling edge. there is no setup requirement between the active edge of the timer trigger and the next rising edge of . if the timer trigger edge occurs closer than a specified minimum setup time to the rising edge of , the down-counter does not begin decrementing until the following rising edge of . if bit 7 in the channel control word is set, the zero-count condition in the down-counter causes a pulse at the channel?s time out pin, and initiates an interrupt request sequence. (for more details, see ?ctc interrupt servicing? on page 27). ctc programming overview to begin counting or timing operations, a channel control word and time constant data word are written to the appropriate channel by the cpu. these words are stored in the channel control or time constant registers of each channel. if a channel has been programmed to enable interrupts, an interrupt vector is written to the appropriate register in the ctc. because of

um008101-0601 counter/timer channels automatic features in the interrupt control logic, one pre-programmed interrupt vector suffices for all four channels. loading the channel control register to load a channel control word, the cpu performs a normal i/o write sequence to the port address corresponding to the desired ctc channel. the ctc input pins cs0 and cs1 are used to form a 2-bit binary address to select one of four channels within the device. (see table 2 on page 5.) in many system architectures, these two input pins are connected to address bus lines a0 and a1, respectively, so that the four channels in a ctc device occupy contiguous i/o port addresses. a word written to a ctc channel is interpreted as a channel control word, and loaded into the channel control register (bit 0 is a logic 1). the other seven bits of this word select operating modes and conditions as indicated in table 2. table 5. channel control register 76543210 interrupt mode prescaler val ue * clk/trg section time trigger* time constant reset control or vec to r r/w r/w r/w r/w r/w r/w r/w r/w bit number field r/w value description 7 interrupt r/w 1 0 enable interrupt disable interrupt 6mode r/w1 0 counter mode timer mode 5 prescaler value* r/w 1 0 256 16 *timer mode only

um008101-0601 counter/timer channels bit 7 = 1. each channel is enabled to generate an interrupt request sequence when the down-counter reaches a zero-count condition. to set the interrupt bit to 1 in any of the four channel control registers an interrupt vector is written to the ctc before operation begins. channel interrupts may be programmed in either counter or timer mode. if an updated channel control word is written to a channel in operation, with bit 7 set, the interrupt enable selection is not retroactive to a preceding zero-count condition. bit 7 = 0. channel interrupts disabled. bit 6 = 1. counter mode selected. the down-counter is decremented by each triggering edge of the external clock (clk/trg) input. the prescaler is not used. bit 6 = 0. timer mode selected. the prescaler is clocked by the system clock , and the output of the prescaler in turn clocks the down-counter. the output of the down-counter (the channel?s zc/to output) is a uniform pulse train of period given by the product as shown below 4 clk/trg edge section r/w 1 0 rising edge falling edge 3 time trigger* r/w 1 0 clk/trg pulse starts timer automatic trigger when time constant is loaded 2 time constant r/w 1 0 time constant follows no time constant follows 1reset r/w1 0 software reset continue operation 0 control or vector r/w 1 0 control ve c t o r bit number field r/w value description *timer mode only

um008101-0601 counter/timer channels where t c is the period of system clock, p is the prescaler factor of 16 or 256, and tc is the time constant data word. bit 5 = 1. defined for timer mode only. prescaler factor is 256. bit 5 = 0. defined for timer mode only. prescaler factor is 16. bit 4 = 1. timer mode: positive edge trigger starts timer operation. counter mode: positive edge decrements the down-counter. bit 4 = 0. timer mode: negative edge trigger starts timer operation. counter mode: negative edge decrements the down-counter. bit 3 = 1. timer mode only. external trigger is valid for starting timer operation after rising edge of t2 of the machine cycle following the one that loads the tune constant. the prescaler is decremented two clock cycles later if the setup tune is met, otherwise three clock cycles. bit 3 = 0. timer mode only. timer begins operation on the rising edge of t2 of the machine cycle following the one that loads the time constant. bit 2 = 1. the time constant data word for the time constant register is the next word written to this channel. if an updated channel control word and time constant data word are written to a channel while it, is already in operation, the down-counter continues decrementing to zero before the new time constant is loaded. bit 2 = 0. no time constant date word for the time constant register is to follow. the channel control word updates the status of a channel already in operation to channel will not operate without a correctly programmed data word in the lime constant register. bit 2 in the channel control word must be set in order to write to the time constant register. bit 1 = 1. counting and/or timing operation is terminated and the channel is reset. this is not a stored condition. the bits in the channel control register are unchanged. if bits 1 and 2 are set to 1, the channel resumes operation upon loading a time constant. bit 1 = 0. channel continues current operation.

um008101-0601 counter/timer channels loading the time constant register a time constant data word is written to the time constant register by the cpu. this event occurs on the i/o write cycle following that of the channel control word. the time constant data word may be any integer value in the range 1-256 (table 6). if all eight bits in this word are zero, it is interpreted as 256. if a time constant date word is loaded to a channel already in operation, the down-counter continues decrementing to zero before the new time constant is loaded. loading the interrupt vector register the z80 ctc operates with the z80 cpu programmed for mode 2 interrupt response. when a ctc interrupt request is acknowledged, a 16-bit pointer is formed to obtain a corresponding interrupt service routine starting address (figure 8). the upper eight bits of this pointer are provided by the cpu?s i register; the lower eight bits are provided by the ctc in the form of an interrupt vector unique to the requesting channel (figure 8). for further details, see ?ctc interrupt servicing? on page 27. the five high-order bits of the interrupt vector are written to the ctc in advance as part of the initial programming sequence. the cpu writes to the i/o port address corresponding to the ctc channel 0. a 0 in bit 0 signals the ctc to load the incoming word into the interrupt vector register. when the interrupt vector is placed on the z80 data bus, the interrupt control logic of the ctc automatically supplies a binary code in bits 1 and 2 identifying which of the four ctc channels is to be serviced. table6.timeconstantregister 76543210 tc7 tc6 tc5 tc4 tc3 tc2 tc1 tc0 r/w r/w r/w r/w r/w r/w r/w r/w

um008101-0601 counter/timer channels figure 8. mode 2 interrupt operation table 7. interrupt vector register 76543210 supplied by user channel identifier word r/w r/w r/w bit number field r/w value description 7?3 reserved r/w supplied by user 2?1 channel identifier r/w 11 10 01 00 channel 3 channel 2 channel 1 channel 0 0word r/w1 0 control interrupt vector service interrupt routine starting address low order high order desired starting address pointed to by: 1reg contents 7bitsfrom peripheral 0

um008101-0601 counter/timer channels ctc timing overview this section describes the timing relationships of the relevant ctc pins for the following types of operation: writing a word to the ctc reading a word from the ctc counting and timing a timing diagram, figure 12, relating to interrupt servicing is found in ?interrupt acknowledge cycle? on page 28. ctc write cycle figure 9 illustrates the timing associated with the ctc write cycle. this sequence is applicable to loading a channel control word, an interrupt vector, or a time constant data word. in the sequence shown, during clock cycle t1, the z80 cpu prepares for the write cycle with a false (high) signal at ctc input pin rd (read). because the ctc has no separate write signal input, it generates its own input internally from the false rd input. during clock cycle t2, the z80 cpu initiates the write cycle with true (low) signals at ctc input pins iorq (i/o request) and ce (chip enable). (see note below.) a 2-bit binary code appears at ctc inputs cs1 and cs0 (channel select 1 and 0), specifying which of the four ctc channels is being written to. at this time, a channel control, interrupt vector, or time constant data word may be loaded to the appropriate ctc internal register in synchronization with the rising edge beginning clock cycle t3. m1 must be false to distinguish the cycle from an interrupt acknowledge. note:

um008101-0601 counter/timer channels figure 9. ctc write cycle ctc read cycle figure 10 illustrates the timing associated with the ctc read cycle. this sequence is used when cpu reads the current contents of the down counter. during clock cycle t2, the z80 cpu initiates the read cycle with true signals at input pins rd (read), iorq (i/o request), and ce (chip enable). a 2-bit binary code appears at ctc inputs cs1 and cs0 (channel select 1 and 0), specifying which of the four ctc channels is being read from. (see note below.) on the rising edge of the cycle t3, the valid contents of the down-counter rising edge of cycle t2 is available on the z80 data bus. no additional wait states are allowed. m1 must be false to distinguish the cycle from an interrupt acknowledge. cs0. cs1, ce iorq rd m1 channel address t 1 t 1 t 2 t wa t 3 note:

um008101-0601 counter/timer channels figure 10. ctc read cycle ctc counting and timing figure 11 illustrates the timing diagram for the ctc counting and timing modes. in the counter mode, the edge (rising edge is active in this example) from the external hardware connected to pin clk/trg, decrements the down- counter in synchronization with the system clock . this clk/trg pulse must have a minimum width and the minimum period must not be less than twice the system clock period. although there is no setup time requirement between the active edge of the clk/trg and the rising edge of ,ifthe clk/trg edge occurs closer than a specified minimum time, the decrement of the down-counter will be delayed one cycle of . immediately after the 1 to 0 decrement of the down-counter, the zc/to output is pulsed true. in the timer mode, a pulse trigger (user selectable as either active high or active low) at the clk/trg pin enables the timing function on the second succeeding rising edge of . as in the counter mode, the triggering pulse is cs0. cs1, ce iorq rd m1 data channel address t 1 t 1 t 2 t wa t 3 clk out

um008101-0601 counter/timer channels detected asynchronously and must have a minimum width. the timing function is initiated in synchronization with . a minimum setup time is required between the active edge of the clk/trg and the rising edge of . if the clk/trg edge occurs closer than this, the initiation of the timer function will be delayed one cycle of . figure 11. ctc counting and timing ctc interrupt servicing overview each ctc channel may be individually programmed to request an interrupt every time its down-counter reaches zero. the purpose of a ctc- generated interrupt is to force the cpu to execute an interrupt service routine. to use this feature the z80 cpu must be programmed for mode 2 interrupt response. in this mode, when a ctc channel interrupt request is acknowledged, a 16-bit pointer must be formed to obtain a corresponding interrupt service routine. the lower eight bits of the pointer are provided by the ctc in the form of an interrupt vector unique to the requesting channel. for further details, refer to the z80 cpu user?s manual. zc/to clk/trg internal counter lead time zero count

um008101-0601 counter/timer channels the ctc?s interrupt control logic ensures that it acts in accordance with z80 system interrupt protocol for nested priority interrupt and proper return from interrupt. the priority of any system device is determined by its physical location in a daisy-chain configuration. two signal lines (iei and ieo) are provided in the ctc to form the system daisy chain. the device closest to the cpu has the highest priority. interrupt priority is predetermined by channel number, with channel 0 having highest priority. according to z80 system interrupt protocol, low priority devices or channels may not interrupt higher priority devices or channels that have not had their interrupt service routines completed. high priority devices or channels may interrupt the servicing of lower priority devices or channels. (for further details, see ?ctc architecture? on page 2.) ?return from interrupt cycle? on page 29 and ?daisy-chain interrupt servicing? on page 30 describe the nominal timing relationships of the relevant ctc pins for the interrupt acknowledge cycle and the return from interrupt cycle. ?daisy-chain interrupt servicing? on page 30 discusses a typical example of daisy-chain interrupt servicing. interrupt acknowledge cycle figure 12 illustrates the timing associated with the interrupt acknowledge cycle. after an interrupt is requested by the ctc, the cpu sends out an interrupt acknowledge (m1 and iorq) . to insure that the daisy-chain enable lines stabilize, channels are inhibited from changing their interrupt request status when m1 is active. m1 is active two clock cycles earlier than iorq and rd is false to distinguish the cycle from an instruction fetch. during this time, the interrupt logic of the ctc determines the highest priority channel requesting an interrupt. if the ctc interrupt enable input (iei) is active, the highest priority interrupting channel within the ctc places its interrupt vector onto the data bus when iorq goes active. two wait states (tw*) are automatically inserted at this time to allow the daisy- chain to stabilize. additional wait states may be added.

um008101-0601 counter/timer channels figure 12. interrupt acknowledge cycle return from interrupt cycle figure 13 illustrates the timing associated with the reti instruction. this instruction is used at the end of an interrupt service routine to initialize the daisy-chain enable lines for control of nested priority interrupt handling. the ctc decodes the two-byte reti code internally and determines whether it is intended for a channel being serviced. when several z80 peripheral chips are in the daisy-chain, iei becomes active on the chip currently under service when an edh op code is decoded. if the following op code is 4dh , the peripheral being serviced is re-initialized and its ieo becomes active. data clk t 1 t 1 t 2 t w *t 3 t w *t 4 vector int iei rd iorq m1

um008101-0601 counter/timer channels figure 13. return from interrupt cycle daisy-chain interrupt servicing figure 14 illustrates a typical nested interrupt sequence that may occur in the ctc. in this example, channel 2 interrupts and is granted service. while this channel is being serviced, higher priority channel 1 interrupts and is granted service. the service routine for the higher priority channel is completed, and a reti instruction is executed to signal the channel that its routine is complete (see ?return from interrupt cycle? on page 29 for further details). at this time, the service routine of the lower priority channel 2 is resumed and completed. ieo clk int iei rd m1 t 1 t 2 t 3 t 4 d 7 ?d 0 *int goes low if more interrupts are pending on the rtc . t 1 t 2 t 3 t 4 t 1 ed 4d

um008101-0601 counter/timer channels figure 14. daisy-chain interrupt servicing iei ieo hi + iei ieo hi + iei ieo hi + iei ieo hi + iei ieo hi iei ieo hi iei ieo hi iei ieo hi iei ieo hi iei ieo hi + iei ieo hi iei ieo hi iei ieo lo iei ieo hi iei ieo hi iei ieo hi iei ieo lo iei ieo lo iei ieo lo iei ieo hi hi lo lo lo hi channel 3 channel 2 channel 1 under service service suspended service resumed service complete 5. second ?reti? instruction issued on completion of channel 2 service routine. 4. channel 1 service routine complete, ?reti? issued, channel 2 serviced resumed. 3. channel 1 interrupts, suspends servicing of channel 2. 2. channel 2 requests an interrupt and is acknowledged. 1. priority interrupt daisy chain before any interrupt occurs. service complete under service channel 0 highest priority channel

um008101-0601 counter/timer channels

um008101-0601 direct memory access direct memory access dma overview direct memory access (dma) and dma controllers are dedicated to controlling high-speed block transfers of data independently of the cpu. dma data transfers are usually between memory and i/o, or vice versa. a dma controller (dmac) also performs some transfers that have tradi- tionally been done by the cpu. for example, the z80 dma can perform memory-to-memory, memory-to-i/o, and i/o-to-memory transfers, as well as search for particular patterns of bits in a byte either simulta- neously with or independently of transfers. the advantages of dma transfers are: transfers bypass the cpu transfers are fast cpu data transfers in systems without dma, data transfers must pass through the cpu and be implemented in software. data transfers through the cpu include executing an instruction sequence for input and output, and tracking each byte of data in the block to be transferred. figure 15 illustrates the minimum sequence of instructions that must be fetched from memory and executed by conventional cpus to transfer a block of data one byte at a time. most cpus require many more instructions. cpu transfers are relatively slow and tie up the cpu. in addition response time (startup time for the first byte) is also usually slow because the i/o device typically uses interrupts to signal its readiness, and the cpu interrupt service routine causes a significant time lag in transferring the first byte.

um008101-0601 direct memory access figure 15. typical cpu i/o sequence the z80 and z8000 cpus both have block-transfer and string-search instructions that can operate on up to 64 kbytes of data with a single instruction. a single block transfer instruction repetitively performs all of the functions illustrated in figure 15 on an entire sequence of bytes. therefore, transfer rates are significantly faster. the 4 mhz Z80A cpu can transfer at about 200 kbytes/sec and the 4 mhz z8000 cpu can reach 800 kbytes/sec. the problem with cpu block transfers in the z80 and z8000 devices is not transfer speed but response time at startup. one of the following methods is normally used to set up executing a block transfer instruction: read source port write to destination port increment address counter increment byte counter no yes end byte count equal block length ?

um008101-0601 direct memory access the i/o device interrupts the cpu and the block transfer instruction is executed in the cpu interrupt service routine. this method has a response time of at least 5 to 10 s, even in 4 mhz Z80A and z8000 devices. the cpu begins executing the device service routine before the i/o device is ready, and a flag bit is constantly polled by the cpu. when the flag bit indicates that the device is ready, the cpu jumps to the block transfer instruction. this method sometimes produces a response time of less than 5 s, but it uses the entire capability of the cpu. the cpu begins executing the block transfer instruction in an interrupt service routine before the i/o device is actually ready. the i/o device idles the cpu with the wait line just after the read and chip-select lines become active. when the i/o device is ready, it releases the wait line and the transfer is completed. this method gives the best response time (250 ns in a 4 mhz Z80A or z8000 cpu) but ties up the bus. both transfer and response times on most cpus are often too slow. while transfer speed can be quite high with the z80 and z8000 cpus, the response time can be too long in interrupt-driven transfer situations. dma data transfers a dma controller (dmac) performs direct data transfers between the source and destination without going through the cpu, and without the instruction fetches required by the cpu. it performs all of the steps illus- trated in figure 15 through hardware. for example, in a memory-to-i/o transfer, the starting address in memory and the length of the block to be transferred are written to the dma by the cpu before to the transfer. the dmac begins transferring data when the cpuenablesthedmacandthereadylinei/oofthedevicebecomes active. in most cases, the cpu is idle during a dma transfer. when the transfer is complete, the dmac signals the cpu and releases control.

um008101-0601 direct memory access dmacs are used when one or more of the following situations or require- ments are present: cpu has too much i/o and cannot perform other tasks properly data transfer must be faster than the cpu can perform transfer response tune (startup) must be faster than the cpu can provide small and low-performance systems generally run without dma. medium-performance systems can also be designed without dma if the cpu can handle transfers fast enough and still perform other operations. when systems require fast transfers or fast response, dmacs are strong candidates for performance enhancement. not only do dmacs transfer faster than most cpus, but the response time is better. response times can even be improved using the techniques described above for cpu response. the following examples are cases in which dma is usually the best choice: disk and diskette controllers scanning operations, such as crt i/o data acquisition memory-to-memory transfers memory searches backup storage (i/o-to-i/o) parallel bus systems such as the ieee 488 fiber optic links block transfers in networking, multiprocessing, or multiprogramming the trade-off for speed is that the cpu typically remains idle and lacks full or partial control of the system bus while the dma is operating. this condition can affect total system throughput, and can also affect such things as memory refresh and other interrupts.

um008101-0601 direct memory access dma characteristics all dmacs are programmable because the cpu must at least write a block length (byte count) and starting memory address to a dmac before they can begin managing a data transfer. the starting address is incre- mented or decremented as the transfer proceeds, and the byte counter is incremented from zero up to the specified block length. in addition to being programmable, dmacs vary in characteristics and capabilities. ports and channels every data transfer has a source and a destination. for example, in memory-to-i/o transfers, memory is the source and i/o is the destination port. the means of controlling and tracking the data exchange between the two ports is called a channel. a channel includes the hardware for address and byte counting, bus control, and coordination of the entire transfer process. the location for each source and destination for a channel is specified either by the dma address-generation mechanism or by hardwiring. the z80 dma generates addresses for both memory and i/o ports during each byte transfer. some dmacs have multiple channels, which means that they can keep track of multiple interleaved transfers, and that one dma can be hardwired to multiple i/o devices. however, because any dma can execute only one read and/or write cycle at a time, multiple channels do not mean higher throughput than single channels in a given speed. the z80 dma is a single-channel device that can generate addresses to perform memory-to- memory data transfers. i/o port addresses on the address bus. the z80 dma can also perform internal byte searches. when the z80 dma loads bytes to an internal dmac register during transfers, the result is that, when a byte is loaded, it can be compared with a maskable control byte.

um008101-0601 direct memory access transfer methods figure 16 compares conventional cpu instructions and the z80 and z8000 cpu block transfer instructions as well as two different methods of dma transfer. this figure compares the read and write cycles to the transfer of a single byte of data. figure 16a illustrates conventional cpu i/o instruction activity. the number of read and write cycles is approximate, some cpus require more cycles. the cpu instruction executes all the steps illustrated in figure 15, plus additional housekeeping tasks. figure 16b illustrates z80 and z8000 cpu block transfer instructions. these instructions are approximate and require more activity than one read cycle and one write cycle after initiation, especially with the z80 cpu. a single block transfer instruction is capable of transferring up to 64 kbytes of data. figure 16c illustrates sequential or flow-through dma transfer where a byte is read from the source port to the dma and then written to the desti- nation port. this method can be implemented on the z80 dma with no external logic in a z80 cpu environment. sequential transfer provides speeds that match or exceed the capability of most serial communication processors and many other i/o or memory devices. figure 16d illustrates simultaneous or flyby dma transfer where a byte is both read and written in the same machine cycle. read and write control lines are both active. source and destination are determined by signals that specify either a memory-read with an i/o-write or an i/o read/memory- write. this is the fastest transfer method, but the external logic required makes timing interfaces to memory and i/o somewhat more complicated. another method used for some dmacs is called a transparent or cycle- stealing transfer. this technique is similar to the instruction in figure 16c, except that control of the bus causes the dma data transfers to be inter- leaved with cpu cycles (dynamic memory is not refreshed). this method

um008101-0601 direct memory access also requires external logic and inhibits memory refresh. additionally, it reduces dma throughput. all dma transfers interrupt dynamic memory refresh by the cpu and most of them idle the cpu. it is, therefore, important to consider these implications when making the trade-off for higher dma transfer speed. figure 16. conceptual comparison of various i/o transfer methods cpu memory i/o cpu memory i/o read/write cycle dma dma d. dma simultaneous transfers c. dma sequential instruction read cycle write cycle bus bus bus cpu memory i/o dma cpu memory i/o dma fetch and read cycles write cycle bus b. z80/z8000 block transfer instruction a. conventional programmed instruction sequence write cycle read cycle

um008101-0601 direct memory access modes of operation within each of the methods illustrated in figure 16c and figure 16d there are up to three modes of operation. these are termed byte, burst, and continuous modes in this manual, although they are also sometimes referred to as single, demand, and block modes. figure 17 illustrates the typical sequence of events for each mode, when the i/o device?s ready signal to the dmac becomes active and before the dma process reaches an end-of-block or other terminating condition. (these figures are expanded in figure 20 through figure 23.) in byte mode, the dmac transfers only one byte at a time while the i/o device ready line is active. control of the system bus is released back to the cpu between each byte. the cpu can then interleave its other activ- ities, until the dma makes a new request to the cpu for system bus control before transferring the next byte. byte mode is related to the transparent method of transfer in that both cause interleaving of cpu and dma func- tions. the byte mode, however, includes the protocol of requesting and releasing the bus for each byte transfer. in burst mode, which is the most common mode, the dmac continues to transfer bytes after gaining control of the system bus until the i/o device ready line goes inactive. during this time, the cpu typically remains idle. when the ready line goes inactive, the dmac releases system bus control back to the cpu. in continuous mode, the dmac holds the system bus until the entire block of data has been transferred. if the i/o device ready line goes inactive before the block is completely transferred, the dmac waits until it becomes active again, but the system bus is not released as in burst mode. the continuous mode is the fastest mode because it has the least response- time overhead when the ready line momentarily goes inactive and returns active again. however, this mode does not allow any cpu activity for the duration of the transfer.

um008101-0601 direct memory access bus control most dmacs do not control the system bus in the same way that a cpu controls it. for example, many dmacs do not have a straightforward interface to the system data bus but rather multiplex a portion of the memory address onto the data bus, from which it must be latched by external logic. nor do most dmacs generate all of the bus control signals that the cpu generates, and therefore they lack some degree of bus control when they operate. the z80 dma is unique among 8-bit dmacs because it generates exactly the same bus control signals for read and write cycles that the z80 cpu does, and also because it has exactly the same logical and electrical interface to the data and address buses as the cpu. this means the other system components cannot discern the difference between the z80 dma and cpu; control by these devices is totally interchangeable. in the sequential dma transfer method (a read cycle followed by a write cycle), it also means that the z80 dma pins can be tied directly to the corre- sponding z80 cpu pins without any of the external interfacing logic that some dmacs require. this property considerably simplifies design and lowers part counts. programmability how a dmac starts, transfers data, and stops is determined by control information written to the dmac by the cpu prior to the transfer. status registers, which can be read by the cpu to determine the transfer condition after the dmac stops transferring, are also typically provided. the degree of programmability is directly related to the dmacs flexibility in handling a variety of transfer tasks. most dmacs are limited in their programmability. the z80 dma, by contrast, has over 140 bits of control information used to tailor the device (and retailor it between operations) for a wide variety of tasks and environments.

um008101-0601 direct memory access for example, the z80 dma can be programmed either to stop, interrupt the cpu, continue, or repeat a transfer when a target event such as an end-of- block, byte match, or ready-line condition is reached. alternatively, its buffered address counters can be reloaded during one byte-mode transfer so that the next transfer can begin quickly at a new location. also, entire read and write cycle timings can be modified independently for each port to fit the requirements of other cpus, memory, or i/o devices that are faster or slower than the standard z80 family timing. this topic, as well as the others described earlier, are expanded in following chapters. they are introduced here to give a generalized framework from whichtolaunchamoredetaileddiscussionofthez80dma. (see also figure 20 through figure 23). figure 17. modes of operation byte (single) burst (demand) continuous (block) yes no yes no release control rdy active ? release control transfer byte request control yes no transfer byte request control transfer byte request control rdy active ? rdy active ?

um008101-0601 direct memory access dma functional description features single highly versatile channel dual port address generation with incrementing, decrementing, or fixed address in both ports buffered address and block-length registers 64 kbyte maximum block length 2.4 or 4 mhz clock rates (z80 or Z80A dma) 1.25 or 2 mb/s data rate (z80 or Z80A dma) transfer, search, or transfer/search operations bit-maskable byte searching sequential (flow-through) or simultaneous (flyby) transfers compatible with z80 and many other cpus byte, burst, and continuous modes auto restart capability variable cycle timing wait-line cycle extension internally modifiable interrupt vectors programmable interrupts on ready, end-of-block, byte match hardware priority daisy-chains for bus requests and interrupts periodic pulse generation for external device 21 writeable control registers seven readable status registers

um008101-0601 direct memory access programmable force ready condition programmable active state for ready line programmable dma enable complete system bus mastering no external logic needed for sequential transfers in z80 environments overview the z80 dma performs data transfers and searches in a wide variety of 8-bit cpu environments. this dma is unique among dmacs because it takes full control of the system address, data, and control buses, and is therefore a special-purpose processor when enabled by the cpu to function in this unique way. the dma also provides complete interfacing to the system bus. for example, in a z80 cpu environment, the z80 dma generates the same signal levels and timings, including tristate control, which the z80 cpu generates to accomplish a transfer. it normally does this without external ttl packages, which other dmas may require. for this reason, and because of its extensive programmability for operating on data and dataflow, the z80 dma can be called a special-purpose transfer processor. it unburdens not only the cpu but also the system designer. the z80 dma is also unique in other respects. first, it generates two port addresses instead of one. because both addresses can be either variable or fixed, the memory-to-memory or i/o-to-i/o transfers can be done with a single channel, whereas other dmacs may require more than one channel or may not do such transfers at all. the capability of the z80 dma?s channel surpasses the capability of any other available monolithic dmac channel to service either fast or slow devices. in addition to having a wait line for extending cycles, the basic

um008101-0601 direct memory access read and write cycles can be programmed for different timing requirements. if multiple channels are needed, multiple z80 dmas can be easily inte- grated. the interrupt structure is fast and versatile. interrupt signals and vectors can be generated under several conditions. finally, the z80 dma passes data through itself and can therefore compare bytes against a bit- maskable match byte. an overview of z80 dma features are listed below and each point is described more thoroughly in this and other chapters. throughout the remainder of this manual the z80 dma is referred to as the dma. this dma is available as either the 2.4 mhz z80 dma or the 4 mhz Z80A dma. both parts have the same features and differ only in speed. programming the z80 dma has 21 writeable 8-bit control registers and 7 readable 8-bit status registers available to the cpu. control bytes can be written to the dma or status bytes can be read from the dma whenever the dma is not controlling the bus. control bytes writeable to the dma include those that effect immediate command actions such as enable, disable, reset, load starting addresses, continue transferring or searching, clear byte and address counters, clear status bits, and more. in addition, many mode-setting control bytes can be written, including the class and mode of operation, port configuration, starting addresses, block length, address-counting rule, match and match- mask bytes, interrupt conditions, interrupt vector, end-of-block rule, ready- line and wait-line rules, and others. readable status registers include a general status byte that reflects ready- line, end-of-block, byte-match, and interrupt conditions, as well as registers for the current byte count and port addresses. there is a full chapter on programming on page 90 that explains these functions in detail, and most of them are described in general terms on the pages that follow.

um008101-0601 direct memory access classes of operation the z80 dma has three basic classes of operation, and two of the classes are each broken into subclasses as follows: transfers of data between any two dma ports: ? sequential transfers (flow-through) ? simultaneous transfers (flyby) searches for a particular bit pattern within a byte at a single dma port combined transfers and searches between any two dma ports: ? sequential transfer/search ? simultaneous transfer/search figure 18 illustrates these classes. the two subclasses of transfers are illus- trated at the top; the search-only class is depicted in the middle, and the two subclasses of transfer-while-searching are featured at the bottom. in all cases, the dma assumes full control of the system address, data, and control buses while transferring or searching a given byte. the dma ports are the source and destination of data; a port is used here to mean either memory or an i/o device. in sequential transfers, which are sometimes called flow-through transfers, each byte transfer includes a read cycle followed by a write cycle. the dma reads the byte via the data bus to an internal register and sustains the byte on the data bus into the subsequent write cycle. in a z80 cpu environment, as well as in certain other cpu environments, sequential dma transfers can be implemented with no external logic between the dma and the cpu. in simultaneous transfers, which are sometimes called flyby transfers, each byte is simultaneously read from the source into the dma and written from the source directly to the destination in a single machine cycle. these transfers, therefore, occur at twice the rate of sequential transfers, but they require at least one external logic package to cause the proper signals to appear simultaneously on the control bus (see ?the actual number of bytes transferred is one more than specified by the block

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um008101-0601 direct memory access figure 19. basic functions of the z80 dma modes of operation within any class of operation, the z80 dma can be programmed to operate in one of three transfer and/or, search modes: byte mode data operations are performed one byte at a time. between each byte oper- ation the system bus is released to the cpu. the bus is requested again for each succeeding byte operation. this is also sometimes called single mode or byte-at-a-time mode. burst mode data operations continue until a port?s ready line to the dma goes inactive. the dma then stops (releases the system bus) after completing its current byte operation. this is also called demand mode. continuous mode data operations continue until the end of the programmed block of data or a stop-on-match condition is reached before the system bus is released. if a dma i /o i/o 1. transfer memory-to-i/o (optional search) 2. transfer i/o-to-memory (optional search) 3. transfer memory-to-memory (optional search) 4. transfer i/o-to-i/o (optional search) 5. search memory 6. search i/o memory 1 2 3 5 4 6

um008101-0601 direct memory access port?s ready line goes inactive before this occurs, the dma pauses until the ready line comes active again. this is also called block mode. in all modes, the operation on the byte is completed in an orderly fashion when a byte of data is read into the dma, regardless of the state of other signals (including a port?s ready line). figure 20 illustrates the sequence of events that occur in a sequential transfer/search of one byte, whatever of the mode of operation. first, the source port address is incremented or decre- mented, if it was programmed to be a variable-address port. then, the byte is read from that port to the dma. next, the destination port address is incremented or decremented, if it was programmed to be a variable. the byte is then written to the destination port. if a search capability is included, the byte is compared to the match byte. when no byte match occurs, the dma increments the byte counter and continues. when a byte is found, a status bit is set and the dma either continues by incrementing the byte counter, stops (releases the bus), or interrupts the cpu, depending on its initial programming. the next three figures illustrate how the three modes function before, during, and after the single-byte operation, which is shown in figure 20. operation in the byte mode (figure 21) begins with an enabling command from the cpu and a test of the i/o device?s ready line. when the ready line is active, the dma requests the system bus (address, data, and control buses) through the bus request line, and the cpu acknowledges and releases control to the dma. the transfer of and/or search of one byte takes place as in figure 20. then, a test is made for end-of-block by checking to see if the byte counter has reached the programmed block length. if the end is not reached, the dma releases the bus back to the cpu. if the end is reached, a status bit is set and some terminating action occurs, according to the initial programming. releasing the bus between each byte allows the cpu to execute at least one machine cycle before releasing the bus again to the dma for the next byte transfer. this means that while the dma operates more slowly than it could in other modes, cpu activities like interrupt acknowledgement, polling, and memory refresh can be inter- leaved with dma transfers in the byte mode.

um008101-0601 direct memory access figure 20. transfer/search one byte byte match ? write data to destination port increment/decrement destination port address read source-port data yes increment byte counter set status flag continue release bus interrupt increment/decrement source-port address no

um008101-0601 direct memory access figure 21. byte mode rdy active ? transfer/search one byte (see figure 20) interrupt release bus auto restart request bus enable dma end ? of block no no yes set status flag yes release bus (cpu executes at least one machine cycle)

um008101-0601 direct memory access figure 22. burst mode in the burst mode (figure 22), the bus is requested in the same manner as previously, but when the dma has control of the bus it continues to transfer bytes until it encounters either an inactive ready signal from an i/o port, an end-of-block, or a byte match as in figure 20. if the ready line goes inactive before end-of-block is reached, the dma releases the bus to the cpu and repetitively tests the ready signal until it comes active again. then it requests the bus again and continues its transfers. because of this, the burst mode is often the most useful one for general-purpose applica- tions. it does not request the bus until it actually can use it, but once it rdy active ? interrupt releasebus auto restart request bus enable dma end ? of block no no yes set status flag no request bus rdy active ? yes yes transfer/search one byte (see figure 20)

um008101-0601 direct memory access attains the bus, the transfers are made at maximum speed. if the transfers are long, however, this mode can interfere with other cpu activities, which come to a halt for the entire duration of dma transfers. in the continuous mode (figure 23), the dma requests the bus in the same manner as other modes and repetitively transfers bytes in the same manner as burst mode. however, unlike the burst mode the bus is retained by the dma whenever an inactive ready signal is encountered prior to a stop on end-of-block or byte match. the dma simply idles, while holding onto the bus, until ready becomes active again. then it completes the transfer sequence. this is the fastest of the three modes because it eliminates the necessity of releasing the bus and requesting it again between complete block transfers. in this mode, however, the system bus is continuously preempted by the dma. this mode is usually used only when very fast transfers are required and when the impact on cpu activities can be tolerated. this might be the case, for instance, when an operating system is beingloadedtomemoryfromdisk. due to the dma?s high-speed buffered method of reading data, operations on one byte are not completed until the next byte is read in. this means that total transfer or search block lengths must be two or more bytes, even in the byte mode, and that block lengths programmed into the dma must be one less than the desired block length. this characteristic is described in detail in internal structure under the section entitled, ?address and byte counting? on page 75.?

um008101-0601 direct memory access figure 23. continuous mode yes rdy active ? interrupt release bus autorestart request bus enable dma end ? of block no no yes set status flag no rdy active ? yes transfer/search one byte (see figure 20)

um008101-0601 direct memory access transfer speed the z80 dma has one of the fastest maximum transfer rates of any 8-bit dmac device. this rate is achieved in the simultaneous transfer class of operation and, unlike the more common sequential transfer class, it requires at least one external ttl package. but because some other 8-bit dmas require some external logic, this constitutes a legitimate speed comparison. table 8 describes the maximum rates that can be achieved in different classes of dma operation. maximum cpu block-transfer rates are also given for comparison. all dma transfers assume the uninterrupted use of burst or continuous mode, and they assume read and write cycles that last two cycles (see ?variable cycle? on page 60). transfer speed in byte mode depends on how long the cpu keeps the bus between each byte transfer of the dma. therefore, the speed is best expressed from the cpu viewpoint. table 9 describes the reduction in z80 throughput (per kilobaud trans- ferred) caused by byte-mode dma transfers, and this rate is compared with the reduction in throughput that would occur if the cpu did its own byte transfers using an interrupt service routine of six instructions (a practical lower limit). ?z80 dma and z80 sio example? on page 139 contains more detail on this data. this data assumes sequential dma transfers with longer cycle timing than the minimum of two clock cycles per read or write. simultaneous transfers of two clock cycles would, therefore, result in even lower impact on cpu throughput. table 8 describes that dma transfer rates in burst and continuous modes can be up to ten times faster than z80 cpu rates. table 9 describes that the reduction of cpu throughput with byte mode dma transfers is about five times less than the reduction that results when the cpu handles its own byte-mode i/o in the normal interrupt mode.

um008101-0601 direct memory access address generation two 26-bit addresses are generated by the dma for every transfer oper- ation: one address for the source port and another for the destination port. the two addresses are multiplexed onto the address bus, according to whether the dma is reading the source or writing to the destination. the two ports are arbitrarily named port a and port b. both a and b can be either source or destination, either memory or i/o, and have fixed or variable addresses. table 8. maximum transfer and search speeds (burst and continuous modes) action z80 (2.4 mhz) z80z (4.0 mhz) dma simultaneous transfer 1.25 mb/s 2.0 mb/s dma search only dma simultaneous transfer/search dma sequential transfer 0.625 mb/s 1.0 mb/s dma sequential transfer/search cpu block transfer instruction 0.125 mb/s 0.200 mb/s table 9. reduction in z80 cpu throughput per kbaud (byte mode transfers) action z80 (2.4 mhz) z80z (4.0 mhz) dma sequential transfer 0.085% 0.041% dma sequential transfer/search cpu interrupt driven transfer 0.340% 0.213%

um008101-0601 direct memory access variable addresses can either increment or decrement automatically from the programmed starting address. fixed addresses are useful for i/o devices and the dmas capability to generate fixed addresses eliminates the need for transfer/search enabling wires to the i/o device (although chip enable hardwiring is still required, as it is with all peripheral circuits). two readable address counters keep the current address of each port. these counters are distinct from the starting address registers for each port, that is, the counters are buffered by the registers. therefore, new starting addresses can be written to the dma whenever the dma is not holding the bus, for example, between byte transfers in byte mode. new starting addresses for a new block of data can be loaded into the dma before the transfer of the current block is finished. loading new starting addresses does not disturb the contents of the associated port address counters. dma address generation capabilities can be used in the following ways: start at a base address and count up or down. automatically step back to the beginning at the completion of an address sequence. load new starting addresses or reload previous ones for the next sequence. byte matching (searching) searches for byte matches can be performed either as a sole function or simultaneously with transfers. when a byte match is found, a status bit in the readable status register is set and the dma can be programmed to do one of the following: stop (release the bus) immediately upon byte match. stop and interrupt the cpu immediately upon byte match. interrupt the cpu when the dma stops at the end of a block.

um008101-0601 direct memory access the match byte written into the dma is masked with another byte so that only certain bits within the match byte can be compared with the corre- sponding bits in the data bytes being searched. interrupts the dma can be programmed to interrupt the cpu on three conditions: interrupt on ready interrupt on byte match interrupt on end-of-block the first condition (i/o-port ready line becoming active) causes an interrupt before the dma requests the bus. the other two conditions cause the dma to interrupt the cpu after the dma stops (releases the bus). stopping the dma on byte match or end-of-block is separately programmed. any of these conditions (ready line becoming active, byte match, or end- of-block) causes a readable status bit to be set. in addition, when an interrupt on any of these conditions is programmed, an interrupt-pending status bit is also set, and each type of interrupt can optionally alter the dmas interrupt vector. the dma shares the z80 family?s versatile interrupt scheme, which provides fast interrupt service in real-time applications. in a z80 cpu environment where the cpu is using its mode 2 interrupts, the dma passes its internally modifiable 8-bit interrupt vector to the cpu, which attaches an additional eight bits to form the memory address of the interrupt routine table. this table contains the address of the beginning of the interrupt routine. in this process, cpu control is transferred to the interrupt routine, so that the next instruction executed after an interrupt acknowledge is the first instruction of the interrupt routine.

um008101-0601 direct memory access auto restart block transfers can be repeated automatically by the dma. this function causes the byte counter to be cleared and the address counters to be reloaded with the contents of the starting-address registers. the auto restart feature relieves the cpu of software overhead for repet- itive operations such as crt refresh and many others. moreover, the cpu can write different starting addresses into the buffer registers during transfers in the byte mode (or burst mode when the ready line is inactive and the bus is released) causing the auto restart to begin at a new location. pulse generation external devices can keep track of how many bytes have been transferred by using the dma?s pulse output, which provides a signal at 256-byte intervals. the interval sequence may be offset at the beginning by 1 to 255 bytes. the interrupt line carries the pulse signal in a manner that prevents inter- pretation by the z80 cpu as an interrupt request, because the signal only appears when the bus request and bus acknowledge lines are both active. under these conditions, the z80 cpu does not monitor the interrupt (int ) line. variable cycle the z80 dma offers the unique feature of programmable operation-cycle length. this is valuable in tailoring the dma to the particular requirements of various cpus and other system components (fast or slow), and in maxi- mizing the data-transfer rate. also, it often eliminates external logic and reduces cpu software overhead. there are two aspects to the variable cycle feature. first, the entire read and write cycles (periods) associated with the source and destination ports can

um008101-0601 direct memory access be independently programmed as 2, 3, or 4 clock cycles long (more if wait cycles are used), thereby increasing or decreasing the speed at which all dma signals change. second, the four signals in each port (i/o request, memory request, read, and write) can each have its active trailing edge terminated one-half clock cycle early. this adds a further flexibility by allowing functions such as shorter-than-normal read or write signals to go inactive before data starts to change. figure 24 illustrates the general capability, which is described laterin?timing?onpage151? figure 24. variable cycle length events and actions table 10 gives an overview of the events that can cause specific actions by the dma, depending on how it is programmed. the events are conditions in the dma?s internal registers, signals from the i/o device, or instructions onthedatabusforwhichthedmawatches. clk t 1 t 2 t 3 t 4 2-cycle 3-cycle 4-cycle early ending for control signals

um008101-0601 direct memory access pin description the following pin descriptions detail the function of the z80 dma external pins as illustrated in figure 25 through figure 28. a15-a0 system address bus (output, tristate). addresses generated by the dma are sent to both source and destination ports, either of which may be main memory or i/o peripherals. table 10. events and actions event actions possible when event occurs end-of-block 1. release bus 2. interrupt cpu 3. auto restart byte match (compare) 1. release bus 2. interrupt cpu 3. continue pulse-control byte matches lower part of byte counter 1. generate pulse ready inactive 1. release bus 2. suspend (continuous mode only) ready active 1. request bus 2. interrupt cpu reti instruction (return from interrupt instruction from the z80 cpu) 1. request bus

um008101-0601 direct memory access bai bus acknowledge in (input, active low). signals that the system buses have been released for dma control. bao bus acknowledge out (output, active low). in multiple-dma configura- tions, this pin signals that the cpu has relinquished control of the bus. bai and bao form a daisy-chain for multiple dma priority resolution over bus control. unlike the interrupt daisy-chain formed with the iei and ieo lines, this chain does not allow preemption of control by a high-priority dma when a lower-priority dma is already bus master. the dma that has the bus is always allowed to finish, regardless of its priority in the chain. busreq bus request (bidirectional, active low, open-drain). as an output, this pin sends requests for control of the system address bus, data bus, and control bus to the cpu. as an input when multiple dmas are strung together in a priority daisy-chain through bai and bao , this pin senses when another dma has requested the buses and causes this dma to delay its bus request until the first dma is finished. because this bidirectional pin allows simul- taneous bidirectional signals with no means of control, no buffers come between this dma and other dmas. there can, however, be buffers between it and the cpu because it is unidirectional into the cpu. a 1.8 kohms pull-up resistor is typically connected to this pin. ce /wait chip enable and wait (input, active low). normally, this functions only as ace line, but it can also be programmed to serve as a wait function. as a ce line from the cpu, this pin becomes active when iorq is active and the i/o port address (up to 16 bits) on the system address bus is the dma?s address, thereby allowing control bytes to be written from the cpu to the dma. as a wait line from memory or i/o devices, after the dma has received a bus acknowledge (busack ) from the cpu, this pin causes wait

um008101-0601 direct memory access states to be inserted in the dma?s operation cycles, thereby slowing the dma to a speed that matches the memory or i/o device. the applications chapter contains a description of how the ce and wait inputs can be multiplexed by the cpu?s busack line. clk system clock (input). this pin is standard z80 single-phase clock at 2.8 mhz (z80 dma) or 4.0 mhz (Z80A dma). for slower system clocks, a ttl gate with a pull-up resistor may be adequate to meet the timing and voltage level specifications. for higher speed systems, use a clock driver with an active pull-up to meet the vih specification and rise time require- ments. there should always be a resistive pull-up to the power supply (10 kohms maximum), ensuring correct power at dma reset. d7-d0 system data bus (bidirectional, tristate). these pins transfer control bytes from the cpu, status byes from the dma, and data from memory or i/o peripherals. data transfers or searches by the dma occur only when the dma controls both this bus and the address bus. when the cpu controls these buses, it can write or read dma control or status bytes. iei interrupt enable in (input, active high). this line, combined with the ieo, form a priority daisy-chain when there is more than one interrupting device. a high on this line indicates that no other device of higher priority is inter- rupting, thereby allowing this dma to interrupt. ieo interrupt enable out (output, active high). ieo is high only when iei is high and this dma is not requesting an interrupt. therefore, this signal blocks lower priority devices from interrupting while a higher priority device is being serviced by its cpu interrupt service routine. unlike devices in a bus-request daisy-chain, devices in an interrupt daisy-chain can

um008101-0601 direct memory access be preempted by higher priority devices before the lower priority device has been fully serviced. int /pulse interrupt request (output, active low, open-drain). this requests a cpu interrupt when brought low while the dma is not the bus master. the cpu acknowledges the interrupt by pulling its iorq output low during an m1 cycle. the dma int pin is typically connected to the int pin of the cpu with a pull-up resistor and tied to all other int pins in the system. this pin can also be used to generate periodic pulses to an external device. it can be used this way only when the dma is bus master, for example, the cpu?s busreq and busack lines are both low and the cpu cannot sense interrupts. iorq input/output request (bidirectional, active low, tristate). used as an input, this pin indicates that the lower half of the address bus contains a valid i/o port address for transfer of control or status bytes from or to the cpu. this dma is the addressed port if its ce pin, iorq pin, and or rd pin are simultaneously active. as an output, after the dma has taken control of the system buses, this pin indicates that the address bus contains a valid 8-bit or 16-bit port address for another i/o device involved in a dma transfer of data. when iorq and m1 are both active inputs to the dma, an interrupt acknowledge by the cpu is indicated. m1 machine cycle one (input, active low). this pin indicates that the current cpu machine cycle is an instruction fetch. this pin has two purposes in the dma?s interrupt structure. first, it is used by the dma to detect return- from-interrupt instructions (reti, or ed4dh) fetched over the data bus by the cpu at the end of interrupt service routines. second, an interrupt acknowledge is indicated when both m1 and iorq are active inputs to the dma. during 2-byte instruction fetches, m1 is active as each op code byte is fetched. in the cmos dma, the m1 signal has a different function:

um008101-0601 direct memory access when m1 occurs without an active rd or iorq for at least two clock cycles, the internal reset is activated at the falling clock after m1 returns to the inactive state. this internal reset lasts for three clock cycles. mreq memory request (output, active low, tristate). this line indicates that the address bus contains a valid address for a memory read or write operation. after the dma has taken control of the system buses, it indicates a dma transfer request from or to memory. rd read (bidirectional, active low, tristate). as an input, this signal indicates that the cpu is ready to read status bytes from the dmas read registers. as an output, after the dma has taken control of the system buses, it indicates a dma-controlled read from memory or i/o port address. rdy ready (input, programmable active low or high). this pin is monitored by the dma to determine when a peripheral device associated with a dma port is ready for a read or write operation. when the dma is enabled to operate, the rdy line indirectly controls dma activity; the manner in which dma activity is controlled by rdy depends on what operating mode is selected (byte, burst, or continuous). an active rdy line can be simulated by programming a force ready condition. this is useful in memory-to-memory operations. it is preferable to have the rdy signal synchronized to the clk signal, for example, rdy should become active on the rising edge of clk. this is particularly important in the continuous mode of operation. wr write (bidirectional, active low, tristate). as an input, this indicates that the cpu is requesting to write control bytes to the dma write registers when the dma is selected. as an output, after the dma has taken control of the

um008101-0601 direct memory access system buses, it indicates a dma-controlled write to a memory or i/o port address. reset reset ( input, active low) is available in the cmos plcc version only. a low in this signal resets the dma. figure 25. pin functions (cmos plcc package only) system control bus system data bus z80 dma clk +5v gnd bao bai busreq d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 system address bus rdy c5 /wait int /pulse iei ieo dma control interrupt control m1 iorq mreq rd wr reset c-mos dma plcc package only bus control

um008101-0601 direct memory access figure 26. 40-pin dip pin assignments
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um008101-0601 direct memory access figure 27. 44-pin plcc pin assignments (z8410 nmos) z8410

um008101-0601 direct memory access figure 28. 44-pin plcc pin assignments (z84c10 nmos) z84c10

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um008101-0601 direct memory access which control bytes can be written to the dma while the cpu has the bus between byte transfers. this allows the next block, which can be an auto restart block, to begin quickly at a new location. notice that the block length counter stops (or auto restarts) as a result of a comparison to the block length register. in changing the register, the block length also changes with what may be unpredictable results. the pulse-control byte illustrated in figure 30 (in the wr4 group) also has a relationship to the byte counter in wr0. the pulse-control byte can be loaded with an offset value between 0 and 255 and this value is continu- ously compared with the lower byte of the byte counter. the nt line generates a pulse each time a match occurs, which happens on every 256 bytes of transfer or search after the initial offset. because the pulse signals generated on the nt line only occur when the dma has control of the system bus, for example, when the busreq and busack lines are simultaneously active, the cpu cannot detect theme and they can be directed exclusively to an external gate, counter, or other device. figure 30 illustrates the seven status registers readable through the data bus. unlike the write registers, the status registers include no second-level registers or groups. these registers are accessed sequentially according to the read mask written to the wr6 group, except that the status byte can be read separately from the other read registers.

um008101-0601 direct memory access figure 30. write register organization (left) and read register organization (right) wrq wr1 wr2 wr3 wr4 wr6 wr5 data bus 7 0 base register byte base register byte base register byte base register byte base register byte base register byte base register byte port a starting address register 15 8 7 0 block length register port a variable timing port b variable timing mask byte match byte 15 8 7 0 port b starting address register interrupt control byte pulse control byte interrupt vector read mask data bus 0 port a address counter byte counter rr4 rr3 rr2 rr1 port b address counter rr6 rr5 status byte rr0 port a address counter (see right illustration) port b address counter (see right illustration) byte counter (see right illustration) status byte (see right)

um008101-0601 direct memory access address and byte counting addresses for either port may be fixed at their programmed starting address, or they may be incremented or decremented from the programmed starting address by the address counters. the block length programmed into the dma is compared with the byte counter, which starts at zero and incre- ments at the completion of each byte operation (figure 20). the dma uses a high-speed buffering or pipelining scheme for reading data. when transferring data and stopping on an end-of-block, the effect of this pipelining is that one more transfer is completed than is programmed into the block-length register; the only exception to this rule occurs in simultaneous transfers that use two-cycle variable timing, in which case two extra bytes are transferred if the ready line remains active. table 11 describes the contents of the counters in the various classes and the modes of transfer involving stopping or interrupting at an end-of-block (interrupts imply prior stopping). search and transfer/search operations that are programmed to stop on byte match function somewhat differently, as described in table 12. matches are discovered only after the next byte is read. in all classes of transfer/search operations, the matched byte is transferred. in simultaneous transfer/search operations, however, an additional byte is usually also transferred. the only exception to this occurs in burst and continuous modes when the ready line goes inactive while the byte match is being located. during simulta- neous transfer/searches in burst or continuous mode, these searches are typically continuous processes performed in memory using a force ready condition or a ready line that will not go inactive. however, when this exception is encountered, the cpu can be programmed to research two bytes when such a match occurs.

um008101-0601 direct memory access notes : * address can increment (+) or decrement (-) from the programmed starting address (as), which is the first address for transfer purposes. ** occurs only in 2-cycle (variable timing) simultaneous transfers when the ready line is still active at the end of the n + 1 byte transfer. *** simultaneous transfers cannot have both ports variable. this class of operation is programmed as a dma search-only operation, with variable addresses ascribed to the programmed source port. what the dma senses is the source port may be either the real source or destination, as determined by external hardware. see ?the actual number of bytes transferred is one more than specified by the block length. * these entries are necessary only in the case of a fixed destination address.? on page 129. table 11. contents of counters after dma stops because of end-of-block (transfer operations) class mode programmed block length bytes transferred at stop byte counter source port address counter* destination port address counter* sequential byte n n+1 n as (n+1) as (n) transfer burst n n+1 n as (n+1) as (n) continuous n n+1 n as (n+1) as (n) search only or simultaneous transfer/search byte n n+1 n as (n+1) *** burst n n+1 n+1 as (n+1) *** burst n n+2** n+1 ** as (n+2)** *** continuous n+1 n+1 n+1 as (n+1) *** continuous n+1 n+2** n+1 ** as (n+2)** *** table 12. contents of counters after dma stops due to byte match (search or transfer/ search operations) class mode match occurs on this byte bytes transferred at stop if transferring byte counter source port address counter* destination port address counter sequential transfer byte m m m-1 as (m) as (m-1) burst m m m-1 as (m) as (m-) continuous m m+ m-1 as (m) as (m -) search only or simultaneous transfer search bytemm mas (m) *** burst m m+1 m+1 as (m+1) *** burst m m** m-1** as (m** *** continuous m m+1 m+1 as (m+1) ***

um008101-0601 direct memory access notes : * address can increment (+) or decrement (-) from the programmed starting address (as), which is the first address for transfer or search. ** occurs only when the ready line is still inactive just prior to the beginning of the last possible cycle in the operation. for example, ready is sampled inactive on the rising edge of clk in the last cycle of the last read operation. *** search only has no destination. simultaneous transfer/search cannot have both ports variable. this class of operation is programmed as a dma search only operation, with variable addresses assigned to the programmed source port. what the dma senses as the source port may be either the real source or destination, as determined by external hardware. see the 'applications' chapter. bus control the dma transfers and searches data by controlling the system buses in the same way that the z80 cpu controls them to perform read and write cycles. specifically, the dma controls the following lines: address bus (16 bits) data bus (8 bits) iorq mreq rd wr in addition, the dma can also be programmed to watch a wait line through its dual-purpose ce /wait pin. continuous m m** m-1** as (m** *** table 12. contents of counters after dma stops due to byte match (search or transfer/ search operations) class mode match occurs on this byte bytes transferred at stop if transferring byte counter source port address counter* destination port address counter

um008101-0601 direct memory access when the dma has requested and received the bus from the cpu, other devices on the system do not perceive the change. the cpu is idle during this time because it cannot fetch instructions from memory. bus requesting two conditions enable the dma to request the bus from the cpu: an enabling command from the cpu, and an active ready condition, resulting from either an active ready line from an i/o device or a force ready command by the cpu. the dma requests the bus by latching its busreq line low. the cpu always responds to a bus request and it does so quickly, in no more than one machine cycle (3 to 10 clock cycles) plus one additional clock cycle by lowering its busack line as an input to the dma?s bai line. both the dma?s busreq output and the cpu?s busack output remain low whilethedmahasthebus. the bus is released back to the cpu when the dma?s busreq line goes high; the cpu?s busack line goes high in the next clock cycle. the dma releases its busreq line in a variety of conditions, including: completion of single-byte transfer (byte mode ready line going inactive (byte and burst modes) byte match (burst and continuous modes) if stop-on-match is programmed end-of-block (all modes), if stop-on-end-of-block is programmed these conditions are explained in the ?timing? chapter. bus requests cannot be made while the cpu services an interrupt from the dma. this is prevented by the interrupt under service (ius) latch, which is discussed later.

um008101-0601 direct memory access bus request daisy-chains multiple dmas can be linked in a prioritized daisy-chain for the purpose of requesting the bus. figure 31 illustrates this procedure. each dma?s busreq pin is bidirectional. as an output, it requests the bus. as an input, this pin senses when another dma in the daisy-chain has requested the bus (brought the busreq line low) and therefore prevents this dma from also requesting the bus until the other dma has finished. any dma that has the bus is always allowed to finish its operation; a higher priority dma cannot preempt it during this time. their proximity to the cpu determines the priority of dmas in a daisy- chain. the dma electrically closest to the cpu (as measured along the busacki /bai lines) has the highest priority. priority matters only when multiple dmas request the bus on the same clock cycle. the higher priority dma can then prevent lower priority dmas from receiving a bus- acknowledge signal through the bai /bao chain. the lower priority dmas continue to hold their busreq lines low until the higher priority dma finishes and releases the bus, thereby allowing lower priority dmas to contend for the bus. figure 31. bus-requesting daisy-chain 1.8k cpu busreq busack dma bai bao busreq dma bai bao busreq

um008101-0601 direct memory access interrupts conditions and methods the z80 cpu prioritizes external events in the following order: 1. bus requests (busreq ) 2. non-maskable interrupts (nmi ) 3. maskable interrupts (int ) in addition to bus requests, the dma normally allows only maskable inter- rupts (int ) and uses them in cpu mode 2, which allows interrupt vectors. non-maskable interrupts are typically reserved for extreme priority events such as power-failure signaling. the dma can be programmed to interrupt the cpu under the following conditions: after the dma?s rdy line has gone active and before the dma requests the bus (interrupt on rdy). on an end-of-block, when the contents of the byte counter match the contents of the block-length register. on a byte match, when the contents of the match-byte register (after masking by the mask-byte register) corresponds to a data byte being transferred or searched. the dma cannot have control of the bus when it interrupts the cpu. signalingontheint line while the dma is bus master generates periodic pulses to an external device. these pulses are not perceived by the z80 cpu. therefore, at stop-on-end-of-block or byte match, the dma first releases the bus before interrupting the cpu, as shown in figure 32. if the dma is programmed to interrupt on end-of-block and also to auto restart on end-of-block, an interrupt occurs (and should be acknowledged for continued operation) at each end-of-block. however, the end-of-block

um008101-0601 direct memory access status bit is not set as it would be without the auto restart. therefore, the interrupt vector cannot indicate the specific interrupt cause, for example, status affects vector is not effective. the z80 cpu acknowledges the interrupt by pulling its m1 and iorq lines low for one machine cycle (see the ?timing? chapter). this causes the dma to put its 8-bit interrupt vector on the data bus, thereby identifying itself and optionally identifying the origin of the interrupt. the cpu uses the vector to access an interrupt service routine, which is then executed. the interrupt service routine typically reenables the dma to request the bus and cause interrupts again. for cpus that have no interrupt acknowledge or a noncompatible one, dma control bytes can be written (usually in the interrupt service routine) to simulate the same functions.

um008101-0601 direct memory access figure 32. z80 interrupt sequence interrupt vectors the z80 cpu interrupt acknowledge cycle causes the dma to put its 8-bit interrupt vector on the data bus (figure 33a). this vector is read by the dma cpu end-of-block or byte match dma releases bus and interrupts cpu cpu acknowledges interrupt dma passes interrupt vector to cpu cpu executes interrupt service routine dma requests bus again * *bus master * * * busreq bai busreq busack int int m1 iorq m1 iorq memory busreq bai busreq busack

um008101-0601 direct memory access cpu to a temporary register. it normally identifies the interrupting device and it can also identify the cause of the interrupt (actually the current state of certain status bits). the i register of the z80 cpu (when the cpu is programmed to mode 2 state) has the upper byte of a 16-bit address, which is formed with the interrupt vector, and this address points to a jump table entryinmemory. the jump table location in memory contains an address that is read to the cpu?s program counter (figure 33b). this address points to the first instruction of the interrupt service routine, which then begins executing. in most dma applications, the cpu?s interrupt service routine contains instructions that write control bytes back into the dma through a register in the cpu (figure 33c). in cpu environments without interrupt vectors, the cpu must poll each peripheral or an external register to determine tristate device interrupted and why.

um008101-0601 direct memory access figure 33. interrupt service routine interrupt latches two primary latches are associated with the interrupt structure: interrupt pending (ip). set whenever the dma requests an interrupt but has not yet acknowledged. it holds the int line low (figure 34). interrupt under service (ius). set when the cpu acknowledges the dma interrupt (figure 35). this accomplishes three things: ? prevents further interrupts by this dma memory cpu dma jump table iregister interrupt vector jump table service routine program counter program counter service routine write registers register a . b . c .

um008101-0601 direct memory access ? prevents interrupts from lower priority devices in an interrupt daisy-chain ? prevents further bus requests by this dma if the interrupt on rdy (interrupt before requesting bus) option is selected, the ip latch is set when the ready line becomes active, causing int to go low. the ip latch is reset whenever the ius latch is se. if the interrupt causing condition is not removed before ius reset, ip becomes set again after ius reset, causing another interrupt. the us latch can be reset by the z80 cpu?s return from interrupt (reti) instruction or by control bytes written to the dma. figure 34. interrupt pending (ip) latch figure 35. interrupt under service (ius) latch reinitialize status byte reset and disable interrupts *note: interrupt conditions can include end-of-block, byte match, or active rdy line, depending on programming. m1 inactive interrupt condition enable interrupts disable interrupts s r q s r ip o interrupt pending (toiuslatchset) s r ius o disable dma reset and disable interrupts reti iei interrupt acknowledge (m1 and iorq ) interrupt pending (from ip latch)

um008101-0601 direct memory access interrupt on ready normally, when the dma has been enabled by the cpu to request the bus while the i/o device?s ready line is inactive, the ready line?s transition to the active state causes the busreq line to go low (figure 65). it does so within two clock cycles if the setup time to the rising edge of clk is met. this does not take place, however, when the interrupt on ready option (also called the interrupt before requesting bus option) is selected. when this option is used, the dma interrupts the cpu when the ready line comes active. the cpu?s interrupt service routine now writes control bytes to the dma, which enable the dma to request the bus after the service routine finishes. as noted earlier, the cpu cannot respond to an interrupt when the dma is bus master. thus, when enabled in continuous mode, the dma inter- rupts the cpu when the ready line first becomes active, but not on succeeding transitions. the interrupt on ready option is typically used to put new starting addresses into the dma, so that transfers go to a part of memory that is dynamically determined. interrupt service routines in addition to the dma?s extensive programmability for mode-setting (usually done at power-up initialization), numerous commands (control bytes) are designed for use in various interrupt service routines. the next chapter on ?programming,? fully explains the commands, but a quick overview follows. some typical functions for which control bytes are available for use in interrupt service routines include: reset the dma ? enable the dma for bus requesting ? disable the dma for bus requesting

um008101-0601 direct memory access reset and disable dma interrupts ? enable dma interrupts ? disable dma interrupts load new starting addresses and block length ? continue prior address counting ? clear block length counter force the ready condition read the status byte ? initiate a status-register read sequence ? clear status interrupt service routines on a z80 cpu always end with a return from interrupt (reti or hex ed4d) instruction, which is now explained. figure 36. interrupt on ready (ior) latch return from interrupt at the end of an interrupt service routine, the z80 cpu executes a return- from-interrupt (reti or hex ed4d) instruction. this returns the cpu from the interrupt service routine. the dma also simultaneously decodes the reti instruction, which it recognizes on the data bus as an instruction (occurring when the dma?s m1 input is low). this causes at least one, and possibly two, events within the dma: d r ior o disable dma cy d-flip-flop +5v interrupt condition (active rdy) enable after reti reset and disable interrupts *note: this latch is only set when the interrupt-on-ready option is selected.

um008101-0601 direct memory access resets the interrupt under service (ius) latch in the dma, thereby allowing its ieo pin to go high so that lower priority devices can interrupt. enables the dma to request the bus again. this occurs only in the interrupt on ready option and only when the enable dma control byte is also used. for non-z80 environments, control bytes are provided to simulate these actions. interrupt daisy-chains multiple dmas can be chained together by their iei and ieo lines, as depicted in figure 37. in the z80 family, the dma?s location in the iei/ ieo chain sets priority. when peripherals simultaneously interrupt the z80 cpu, the highest priority peripheral (nearest the +5v end of the daisy-chain) is serviced. the cpu receives the winning peripheral?s interrupt vector. the iei/ieo chain allows only the highest priority interrupting peripheral to place its interrupt vector on the data bus. in non-z80 environments that have no interrupt vectors, the winning peripheral is determined by successively reading the status of all peripherals. for a device to have priority, its iei line must be high. when a device needs service, it prevents downstream devices from interrupting by pulling its ieo line low. the next device in the chain then passes this low condition on to other downstream devices by pulling its ieo line low, and so on. whenever an interrupt is acknowledged (figure 32), the cpu?s interrupt structure is disabled. it must subsequently be reenabled by an enable inter- rupts instruction before other devices can interrupt again. this normally takes place within the interrupt service routine. when done early in the service routine, this permits higher priority peripherals to interrupt the cpu while the latter is still executing that service routine. thus, nested interrupts

um008101-0601 direct memory access are allowed in which the higher priority peripheral suspends the execution of the lower priority peripheral?s service routine. bus-requesting daisy-chains do not have this preemption or nesting ability. instead, any peripheral that is able to get the bus keeps it until task completion. figure 37. interrupt daisy-chain polling for service requests when the cpu cannot detect interrupts directly, it polls an external gate as shown in figure 38. polling is accomplished in the following way: enable the dma?s interrupt structure with a control byte poll a status bit to see when an interrupt request occurs +5v z80 cpu int iei int ieo int highest priority interrupting device iei ieo to lower priority interrupting device dma tristate enable line, normally at tristate, for example, connected to a chip select decoder. pending polling cpu int

um008101-0601 direct memory access figure 38. polling for a service request bit programming overview the dma must be programmed before use. its control registers have no useful default values at power-up. in addition, commands are frequently written to the dma after the initial power-up programming sets basic dma operating modes; this is most commonly done within service routines for purposes such as reading status, changing starting addresses, and reenabling both interrupt and bus-request logic after a block transfer or search. the dma has two primary states that can be set: (1) an enabled state, in which the dma gains control of the system buses and directs data transfers between ports or data searching from a single port; and (2) a disabled state, in which the dma initiates neither bus requests nor data transfers. table 13 describes these states and their substates in detail. when the dma is powered-up or reset by any means, it is automatically placed into the disabled state. program commands can be written to it by the cpu in the enable/inactive state, but this automatically puts the dma into the disabled state, which is maintained until an enable dma command is written by the cpu to the dma?s write register 6 (wr6). in the z80 family, the dma normally exists as a peripheral device in system i/o space. its chip enable (ce ) signal is decoded from the lower byte of the address bus for this purpose and all control bytes and status bytes are written to and read from the same i/o port address, using an output instruction such as otir (in the z80 cpu). it is possible to use the dma in memory mapped i/o structures, but this involves some external logic, which is explained in the ?applications?

um008101-0601 direct memory access chapter. it is not possible for the dma to program itself by directing transfers of control bytes from memory to its own internal registers. when dma interrupt vectors are used in a z80 environment, the z80 cpu should be programmed for mode-2 maskable interrupts. table 13. dma status disabled enabled active inactive (stopped) suspended operating description dma cannot request the bus (cannot pull its busreq input to cpu low). dma can request the bus and may have had the bus immediately prior to this state, but it is not currently the bus master. dma is bus master but no operations are taking place. dma is bus master and is transferring and/ or searching in one of three modes: byte, burst, or continuous can the cpu write dma control bytes or read dma status bytes? yes yes, but first write a disable dma command no no external actions that cause the state power-down end-of-block in any mode, except with auto restart. byte match in any mode. byte or burst mode bai line inactive. loss of power. rdy line inactive in continuous mode. rdy line active in burst mode, if dma is enabled. reti instruction fetched by cpu, if dma is enabled and rdy line is active. dma commands (wr6 control bytes) causing the state any command except the enable dma command. (and the reinitialize status byte command, if it is not preceded by another command.) the disable dma command is specifically designed for this situation. enable dma if rdy line is inactive and the force ready command is not used. enable dma, if rdy line is inactive in continuous mode. enable dma, if rdy is active or the force is used and the command is outside an interrupt service routine.

um008101-0601 direct memory access write registers control bytes must be written to all relevant registers in the dma at power- up initialization. this section describes and illustrates each of the write registers, wr0 through wr6, to which control bytes can be written. the convention of calling the control bytes written to wr6 ?commands? is often used, because they are commonly used within cpu interrupt service routines and at other times during system operation in addition to their use at power-up initialization of the dma. ?internal structure? on page 71 gives an organizational overview of the write registers (figure 30) and describes the access method. control bytes are written to one or more of the write register groups (wr6-wr0) by first writing a byte to the ?base register? in that group. all groups have base registers and most groups have additional associated registers. the asso- ciated registers in a group are sequentially accessed by first writing a byte to the base register. the base register byte contains both control bits for dma function control, and pointer bits (1s) to one or more of the asso- ciated registers in the base register?s group. figure 39 for wr0 illustrates this. in this figure, the sequence in which associated registers within a group can be written to is shown by the vertical position of the associated registers. for example, if a byte written to the dma contains the bits that identify wr0 (bits d0, d1, and d7), and also contains 1s in the bit positions that point to associated registers 2 and 4, then the next two bytes written to the dma after the base register byte is stored in these two associated registers, in that order. figure 40 through figure 46 illustrate and describe each of seven base registers and their associated registers. these figures, unlike figure 30, do not include the 16-bit counters associated with the starting-address and block-length registers.

um008101-0601 direct memory access figure 39. write-register pointing methods write register 0 group the wr0 base register byte is identified by a 0 in bit 7 and any combi- nation except 0, 0 in bits 0 and 1 (figure 40). it sets the following condi- tions. class of operation bits 1 and 0 used together set the class of operation as sequential transfer (0,1), search only (1,0), or sequential/transfer/search (1,1). simultaneous transfers or transfer/searches are obtained by selecting the search-only class (1,0) and by allowing the external hardware to generate the appro- priate bus control signals for the complete transfer (see the chapter ?applications?). d7 d6 d5 d4 d3 d2 d1 d0 base register associated register #1 associated register #2 associated register #3 associated register #4 pointer bits

um008101-0601 direct memory access source and destination bit 2 indicates the source port and, by implication, the destination port, if the operation is a sequential transfer. when bit 2 is 0, port b is the source; when bit 2 is 1, port a is the source. search-only operations have only a source port. if the operation is a simultaneous transfer or transfer/search (where the class is set to search-only), external hard wiring determines the destination port. the direction of transfer should only be changed from its current setting after the dma is disabled by writing some other control byte to it. therefore, the wr0 byte should not be the first byte written to the dma if changing the direction of transfer. port a starting address if port a is used for either source or destination, its starting address must be programmed. set bits 3 and 4 in the base register byte to 1 so that the next two bytes written to the dma are recognized as the low and high bytes, respectively, of the port a starting address. this address is interpreted in the context of the entries in wr1 bits 3 through 5, which differentiate the address as either memory or i/o, fixed or variable, and, if variable, incre- menting or decrementing. if port a is to be a fixed address destination port, see the section following entitled ?fixed-address destination ports.?

um008101-0601 direct memory access figure 40. write register 0 group block length all operations must have a declared block length because the default values at power-up are unpredictable for block length. these registers are written to by setting pointer bits 5 and 6 in the wr0 base register byte. the block length can be up to 64 kbytes. due to the pipelining method of reading in data, the number of bytes actually searched or transferred may be one or two more than the number entered here. ?address and byte counting? on page 75 in ?internal structure? on page 71 describes this (table 11). programming a block length of zero results in the transfer or search of 216 + 1 bytes. therefore, the shortest block length that can be entered is 1, which usually results in a transfer or search of two bytes (table 12). d7 d6 d5 d4 d3 d2 d1 d0 base register byte port a starting address (low byte) port a starting address (high byte) block length (low byte) block length (high byte) 00 0 1 1 1 0 1 do not use =transfer =search = search/transfer 0 =portb port a 0 =porta port b

um008101-0601 direct memory access write register 1 group bits 7, 2, 1, and 0, as figure 41 illustrates, select the base register byte for this group. the group is used only when port a is used, for example, do not program it for a search only, simultaneous transfer, or simultaneous transfer/ search with port b as the source. it specifies the following characteristics: device type (port a) bit 3 identifies port a as either memory or i/o. this specification causes the proper control line mreq or iorq to come active for cycles involving that port. variable/fixed addressing (port a) bits 4 and 5 specify whether the port a address increments, decrements, or remains fixed for each byte of data transferred or searched. the first byte of data in an operation uses the starting address entered for port a in wr0. incrementing or decrementing begins on the second byte of the operation. variable cycle (port a) if bit 6 is set to 0, the dma?s variable-cycle timing feature is not used; instead, standard z80 timing for read and write cycles is used, which is described in the ?timing? chapter. if bit 6 is set to 1, the next byte written to the dma after the wr1 base register byte is the port a variable-timing byte. this allows the length of the port?s read and write cycles to be shortened. the choices for overall cycle timing of the dma, including activation of the iorq ,mreq ,rd ,andwr lines, are specified in bits 1 and 0 as follows: 4 clock cycles 3 clock cycles 2 clock cycles

um008101-0601 direct memory access in addition, bits 7, 6, 3, and 2 of the variable-timing byte allow termination of various lines 1/2 cycle earlier than specified in bits 1 and 0. the chapter on ?timing? illustrates and describes the effect of this in detail. particular note must be taken of the iorq line when variable-cycle timing is used in sequential transfers or transfer/searches. in i/o-to-memory or memory-to-i/o operation, the memory port must be programmed to allow its iorq line to end early. (the iorq line normally has nothing to do with memory). however, this requirement does not apply to the cmos dma counter controller. if an i/o-to-i/o operation is being performed, both ports must have their iorq lines end early. when the variable-timing feature is employed the iorq line changes logic levels off a different clock cycle edge than the other control lines. figure 41. write register 1 group d7 d6 d5 d4 d3 d2 d1 d0 base register byte 00 0 1 1 1 0 1 = port a address decrements 0 = port a is memory 0 = port a is i/o port a variable 00 0 1 1 1 0 1 = cycle length = 3 = cycle length = 2 =donotuse = port a address increments = port a address fixed timing byte = cycle length = 4 wr ends 1/2 cycle early = 0 rd ends 1/2 cycle early = 0 mreq ends 1/2 cycle early = 0 0=iorq ends 1/2 cycle early 00 00 1 0

um008101-0601 direct memory access write register 2 group bits 7, 2, 1, and 0, depicted in figure 42, specify the base register byte for this group. the group is used only when port b is used, for example, do not program it for a search-only, simultaneous transfer, or simultaneous transfer/search with port a as the source. its syntax is the same as wr1. figure 42. write register 2 group write register 3 group bits 7, 1, and 0, depicted in figure 43, specify the base register byte for this group. the group is used primarily to specify the stop-on-match condition as well as the specific match byte for a search operation. it can perform fast, one-byte enabling of both bus requests and interrupts. a description of its functions follows. d7 d6 d5 d4 d3 d2 d1 d0 base register byte 00 0 1 1 1 0 1 = port b address decrements 0 = port b is memory 0 =portbisi/o port b variable 00 0 1 1 1 0 1 = cycle length = 3 = cycle length = 2 =donotuse = port b address increments = port b address fixed timing byte = cycle length = 4 wr ends 1/2 cycle early = 0 rd ends 1/2 cycle early = 0 mreq ends 1/2 cycle early = 0 0=iorq ends 1/2 cycle early 00 0 0

um008101-0601 direct memory access stop on match setting bit 2 of the base register byte to 1 causes the dma to stop and release the bus when a data byte matches the match byte, which is described later. a search or transfer/search operation must be specified in wr0 to make this bit valid when set. if this bit is 0 (no stop on match), a status flag is still set in the status byte when a match occurs and there still remains the option of interrupting on match (see wr4). no stop or interrupt on match in the search class is used to obtain simultaneous transfers without searching actions. match byte when bit 4 of the base register is set to 1, the match byte that is compared with every data byte searched must be specified. a search operation must be specified in wr0 to make this bit valid, as shown in the following function. mask byte when bit 3 is set to 1, the mask byte must be subsequently specified. bit positions that contain 1s in the mask byte cause comparisons at those same bit positions in the match byte (see preceding paragraph) to be ignored. for example, if the mask byte is 00001111, only the high four bits of the match byte is compared to the data bytes being searched. interrupt enable a 1 in bit 5 of the base register enables the dma to generate an interrupt. this function duplicates the enable interrupts command in wr6.

um008101-0601 direct memory access dma enable a1 in bit 6 of the base register enables the dma to request the bus. this function duplicates the enable dma command in wr6 and is used as the last control byte written to the dma prior to allowing the dma to usurp the bus from the cpu. the enable dma command is often better for this purpose. figure 43. write register 3 group write register 4 group bits 7, 1, and 0, which figure 44 shows, select the base register byte for this group. the group specifies the following characteristics: operating mode bits 6 and 5 of the base register specify the operating mode as byte, burst, or continuous. for a review of these modes, see figure 41 through figure 44, table 13 and table 15. d7 d6 d5 d4 d3 d2 d1 d0 base register byte mask byte (0 = compare) 00 0 dma enable = 1 interrupt enable = 1 1 = stop on match match byte

um008101-0601 direct memory access starting address (port b) the starting address for port b in the next two bytes may be specified by setting bits 2 and 3 of the base register to 1. this is only needed if port b is used, and then it specifies the first address at which a byte is read from or written to, depending on whether the port is declared a source or destination in wr0. if port b is to be a fixed-address destination, see ?fixed-address destination ports? on page 121. interrupts bit 4 of the base register byte can point to the interrupt control byte, and bits 4 and 3 of the interrupt control byte can point to the interrupt vector and pulse control bytes, respectively. the interrupt control byte also specifies one or more of the following three interrupt conditions: interruptonmatch(bit0),ifstoponmatchorstoponend-of-blockis also programmed interrupt at end-of-block (bit 1), if stop on end-of-block is also programmed interrupt on ready (bit 6), for example, interrupt before requesting the bus when the ready line becomes active setting any of these bits to 1 enables the interrupt condition but not the interrupt circuitry itself, which is enabled either through the enable interrupts command in wr6 or through bit 5 in wr3. interrupts do not occur on these conditions if their associated bits are 0 in the interrupt control byte. table 13 and table 15 in the previous chapter apply to these interrupt conditions because the dma releases the bus (stops) before inter- rupting the cpu.

um008101-0601 direct memory access interrupt vector bit 4 of the interrupt control byte allows the interrupt vector to be entered. in addition, when bit 5 of the interrupt control byte (status affects vector) issetto1,bits1and2oftheinterruptvectoraremodifiedtoreflectthe cause of the interrupt (for example, the state of the ready line or status latches) before the vector is placed on the data bus in response to the cpu?s interrupt acknowledge. the status affects vector mode must not be used when both auto restart and interrupt on end-of-block have been programmed. the interrupt vector sent at the end of each block in this case cannot be modified to reflect the end-of-block status. pulse generation pulse generation is caused by (1) pointing to the interrupt control byte with the base register byte, (2) setting bits 2 and 3 of the interrupt control byte, and (3) entering an offset value in the pulse control byte. the pulse control byte is compared with the lower byte of the byte counter and a pulse is generatedontheint line whenever a match occurs, which is every 256- byte transfers or searches after the initial offset number of bytes.

um008101-0601 direct memory access figure 44. write register 4 group write register 5 group bits 7, 6, 2, 1, and 0, illustrated in figure 45, specify the base register byte for this one register group. the byte is used to specify these characteristics: d7 d6 d5 d4 d3 d2 d1 d0 base register byte 0 0 0 0 = interrupt on end-of-block = interrupt on match and end-of-block = interrupt on rdy 01 1 port b starting address pulse control byte interrupt on rdy = 1 status affects vector = 1 1 = pulse generated interrupt vector 0 0 0 0 modified as shown only if status affects vector bit is set vector is automatically 1 = interrupted at end-of-block 1 = interrupted on match 0 interrupt control byte (high byte) port b starting address (low byte) 0 1 0 1 0 0 1 1 continuous = burst = do not program = byte = = interrupt on match

um008101-0601 direct memory access end-of-block action bit 5 specifies either a stop (bus release) or an auto repeat at the end of the blocklengthprogrammedinwr0.tointerruptattheendofablock (wr4), bit 5 should be 0 because the dma must reset the end-of-block status bit to proceed with a new block. in auto restart, the end-of-block status bit is also reset. ce /wait line use bit 4 specifies that the dma?s ce /wait line is to be used in one of two ways: ce only the ce /wait line functions only as a chip enable line, allowing cpu writing and reading of control/status bytes when the dma is not bus master. see the ?applications? chapter for the method by which this time is decoded from the address bus. ce /wait multiplex this line functions as described in ?ce only? above, when the dma is not bus master. when the dma has the bus, however, the line allows external wait inputs from external logic to extend the dma's cycle programmed in wr1 and/or wr2. see the ?applications? chapter for hardware interfacing of this option. ready-line state bit 3 specifies that the dma interprets the ready (rdy) line as active when high or active when low. this allows flexibility in interfacing to a variety of other devices.

um008101-0601 direct memory access figure 45. write register 5 group write register 6 group the base register byte for this group has bits 7, 1, and 0 set to one, which figure 46 depicts. the remaining bits specify 16 commands that are commonly used after dma initialization (for example, within cpu interrupt service routines), and to point to a read mask for the read registers. each of these commands, except the enable dma command, disables the dma. therefore, the enable dma command must be the last command written before dma bus requests can begin. reset (c3) this command is used at power-up and when aborting a program sequence to do the following: disable interrupt and bus-request logic reset interrupt latches unforce a force ready condition reset the auto repeat function (see wr5) reset the wait function (see wr5) d7 d6 d5 d4 d3 d2 d1 d0 base register byte 0 = ready active low 1 = ready active high 10 0 10 0 = stop on end-of-block 1 = auto restart on end-of-block 0 =ce only 1 =ce /wait only

um008101-0601 direct memory access reinitialize ports a and b to standard z80 cycle timing (see wr1 and wr2) at power-up, one reset command is sent to the dma prior to the initial- ization program. when aborting an operation sequence, sending six reset commands guarantees resetting (this is because wr4 has five associated registers that can potentially be pointed to). the reset command does not perform a complete dma reset. for example, it does not reset the read sequence, which is set by the initiate read sequence command. resetportatiming(c7) resets the port a variable timing byte in wr1 to standard z80 timing. the reset command also perform this function. resetportbtiming(cb) resets the port b variable timing byte in wr2 as described in reset port a timing (c7). load (cf) this command must be used to write new addresses to the address registers (wr0 and/or wr4) or to restart an operation (except auto restart) at the same addresses. it loads the contents of both starting-address registers to their associated address counters (figure 30). it also clears the byte counter associated with the block-length register, and it unforces an internal force ready condition. the starting addresses must be written in wr0 and/or wr4 before the load command is written, if they are to differ from the previous starting addresses. only the source-port address counter is immediately loaded. the desti- nation-port address counter (if used) is loaded during the first count of the destination-port address. if the destination-port address is fixed, this indi-

um008101-0601 direct memory access cates that it is never loaded. this special situation is discussed in a later section entitled ?fixed-address destination ports.? if the dma is in an inactive state (table 15) when the load command is written, another dma control byte must precede the load. any other command, such as disable dma, serves this purpose. because load unforces a forced-ready condition, the load must precede a force ready command when the latter is used. continue (d3) this command clears the byte counter to zero but leaves the address counters of both ports with their current contents. transfers or searches continue from where they left off after an enable dma command, although the byte count starts over. the continue command is typically used to transfer several blocks to consecutive locations in memory when it is desirable to know when each block has finished transferring. specifically, an interrupt at the end of each block may be needed. use this command rather than a load command to transfer the next block after the interrupt. a new block length can be entered in wr0 in conjunction with the continue command. if the dma is in an inactive state (figure 15) when the continue command is written, another dma control byte must precede the continue. any other command, such as disable dma, serves this purpose. disable interrupts (af) the command is used in non-z80 cpu environments to simulate the z80 cpu?s automatic interrupt acknowledge to the dma. when the dma interrupts a non-z80 cpu, the cpu writes a disable interrupts to the dma early in the service routine. this allows the int line to go inactive but prevents the dma from sending subsequent interrupts while

um008101-0601 direct memory access the routine is being executed. near the end of the routine, the cpu writes an enable interrupts command to the diva, which enables it to generate a new interrupt. this command is less extensive than the reset and disable inter- rupts command because it does not reset the interrupt pending (ip) and interrupt under service (ius) latches. figure 46. write register 6 group d7 d6 d5 d4 d3 d2 d1 d0 base register byte 0 1 11 1 =c3=reset 000 hex command name 0 1 =c7=resetportatiming 001 0 1 =c8=resetportbtiming 010 0 1 = cf = load 011 0 1 = d3 = continue 100 1 0 = af = disable interrupts 011 1 0 = ab = enable interrupts 010 1 0 = a3 = reset and disable interrupts 000 1 0 = b7 = enable after reti 101 1 0 = bf = read status byte 111 0 0 = 8b = reinitialize status byte 010 1 0 = a7 = initialize read sequence 001 1 0 = b3 = force ready 100 0 0 =87=enabledma 001 0 0 = 83 = disable dma 000 1 0 = bb = read mask follows 110 read mask (1=enable) status byte byte counter (low byte) byte counter (high byte) port a address (low byte) port b address (high byte) 0 port b address (low byte) port a address (high byte)

um008101-0601 direct memory access enable interrupts (ab) see the preceding description of disable interrupts. a z80 cpu environment uses this command at power-up to enable the interrupt logic at the beginning (the dma comes up with this logic disabled). it is not needed, however, to enable subsequent interrupts because this function is provided for by the cpu?s fetching and the dma?s decoding of the reti instruction. the only exception is when the disable interrupts command is used; the enable interrupts command must also be used to begin dma operations again. any conditions selected to cause an interrupt are latched in the dma even when interrupts are disabled. they can then cause a later interrupt after interrupts are reenabled. the enable interrupts command must not be written until after the dma has been configured and the reinitialize status byte command has been written. this command has the same effect as writing a 1tobit5ofwr3. reset and disable interrupts (a3) this command is useful in cpu environments such as the 8080 and 8085 where there is an interrupt acknowledge function but no reti instruction, as in the z80 cpu. this command accomplishes four functions: resets the interrupt under service (ius) latch resets the interrupt pending (ip) latch unforces an internal force ready condition disables further interrupts by the dma (same as the disable interrupts command) in the non-z80 environment just described, it would be used as follows: after the dma interrupt is received and acknowledged, the interrupt vector is sent to the cpu, which branches to the service routine. near the

um008101-0601 direct memory access end of the service routine, the cpu writes a reset and disable interrupts command, then an enable interrupts command, and then an enable dma command before executing its return-from- interrupt instruction. this command, when followed by an enable interrupts command, takes the place of the z80 reti instruction. it is not needed in a z80 envi- ronment. because reset and disable interrupts unforces a forced-ready condition, the reset and disable interrupts must precede a force ready command when the latter is used. enable after reti (b7) thiscommandisusedonlywhenthedmaisoperatedintheinterrupton ready mode (programmed in wr4). it enables the dma to request the bus again after returning from an interrupt. this command is always used in z80 cpu environments to get further bus requesting after an interrupt on ready. it is sometimes used in other environments, such as the 8080. an interrupt on ready (ior) latch is set during such an interrupt. this latch prevents the dma from requesting the bus from the time the ready line goes active until the time the latch is reset by the enable after reti command (in z80 and some other environments, there is an overlap in bus- request prevention by the ior and the ius latches). in a z80 cpu interrupt service routine, the order of dma commands and cpu instructions must be: 1. 2. 3. 4. enable after reti command 5. enable dma command

um008101-0601 direct memory access 6. 7. 8. reti instruction read status byte (bf) this command causes the next cpu read of the dma to access the status byte, which is illustrated in ?read registers? on page 114. if other read registers are being read, the sequence of reading (as defined by the read mask) must be completed before issuing this command. reinitialize status byte (8b) this command reinitializes bits 4 and 5 of the status byte. after reinitial- ization, the status byte looks like this: the disable dma or any other command must be used before the reinitialize status byte command after having stopped on end-of- block or byte match. due to a potential hardware race condition internal to table 14. reinitialize status byte bit value meaning 0 i/o dma operation has/has not occurred 1 i/o ready line active/inactive 2 x undefined bit 3 0/1 interrupt pending/not pending 4 1 match not found 5 1 not end-of-block 6 x undefined bit 7 x undefined bit

um008101-0601 direct memory access the dma, reinitialization of the status bits may remove the condition that stopped the dma and the dma might immediately request the bus again if it is not disabled. (the reinitialize status byte command in wr6 is similar in this respect to the wr0 byte when transfer direction is being changed: both of these control bytes must be preceded by some other control bytes to ensure that the dma is disabled.) the interrupt pending status (bit 3) of the status bytes can be reinitialized by acknowledging the interrupt, servicing it, and writing a reset and disable interrupts command. the dma operation status (bit 0) can be reinitialized with a load command. read mask follows (bb) this command points to the read mask (figure 46). it allows the next control bytewrittentothedmatogotothereadmaskregister.thereadmaskis used to set a new sequence, for reading the read registers, rr0 through rr6, and it is normally part of the power-up initialization of the dma. the read registers are always read in a fixed sequence beginning with rr0 and ending with rr6. however, the registers read in this sequence can be limited by programming the read mask. the read mask is programmed with 1s in the bit positions associated with the registers to be read. for example, if the read mask contains 0001 1001 , the following read registers are read in the following order: 1. status byte (rr0) 2. port a address counter, low byte (rr3) 3. port a address counter, high byte (rr4) when the read mask has been programmed, it must be initialized to begin at the lowest-order register selected. do this with the initiate read sequence command.

um008101-0601 direct memory access initiate read sequence (a7) this command initiates the read-sequence pointer command, allowing the next cpu read instruction to the dma access to the first (low-order) read register designated as readable by the read mask. when started, the read sequence specified by the read mask must be completed before, for example, giving another initiate read sequence or a read status byte command. registers do not need to be read immediately after writing the initiate read sequence command. other commands (except initiate read sequence and read status byte ) can be written and can go through bus-request/bus release cycles before executing the first read and subse- quent reads. force ready (b3) this command, in burst or continuous mode, forces an internal ready condition to take the place of an external active ready signal. it is used for memory-to-memory transfers and memory searches where no ready line is necessary. ready active high/low (bit 3 of wr5) need not be considered when this command is used. the force ready condition is unforced by the following commands and conditions: reset command load command reset and disable interrupts command end-of-block termination byte-match termination bus release by dma because bus release by the dma unforces the ready condition, this command allows the dma to transfer only one byte in the byte mode.

um008101-0601 direct memory access enable dma (87) this command allows the dma to request the system bus and proceed with its operation if all other functional conditions are met, for example, if the ready line is active or the force ready condition is present. this command, and bit 6 of wr3, are the only control bytes that do not disable the dma. all other control bytes written to the dma automatically disable the dma. therefore, the enable dma command is always required as the last command after writing or reading any other bytes to or from the dma. this command enables the dma?s bus request logic. it does not affect interrupt logic and it does not reset any functions or latches. this bus- request-enabling function is duplicated in bit 6 of wr3. in an interrupt service routine, the enable dma command must be the last command to the dma before the cpu executes its return-from- interrupt instruction. disable dma (83) this command prevents the dma from requesting the bus. it is used to stop dma action for external reasons, such as a pending power-out, and in the special case of reinitializing the status byte after a stop on end-of-block or a stop on byte match (see the reinitialize status byte command). read registers process read registers by first writing a command to the dma, then by reading either immediately or later. accomplish cpu reads by addressing the dma as an i/o device using input instructions (such as inir for the z80 cpu). commands written to the dma can be either of the following:

um008101-0601 direct memory access read status byte this command causes the next cpu read of the dma to access the status byte, which is the first read register. initiate read sequence this command initializes access to a repeatable series of reads that follow the sequence defined in the read mask. these commands are described in the immediately preceding pages, and figure 46 illustrates the read mask. as mentioned in the description of these commands, the reading of registers do not need to be contiguous in time with these write commands or with other cpu read instructions accessing registers in the same read sequence. two other commands are also related to the read registers: reinitialize status byte this command reinitializes bits 4 and 5 of the status byte to 1s. read mask follows this command allows the read mask to be programme. figure 47 illustrates more clearly the group of the seven read registers in relation to the write registers. the read registers include: status byte (rr0) the status byte can be read independently from the other read registers and two of its bits can be reinitialized to identify end-of-block and match bytes. the bits in the status byte are defined as follows:

um008101-0601 direct memory access bit 0 indicates whether the dma has requested the bus after the fast load command. 1 indicates yes, 0 indicates no. bit 1 indicates whether the dma?s rdy pin currently has a signal input that is defined as active by bit 3 of wr5. 1 indicates an active ready line. 0 indicates an inactive ready line. bit 2 undefined. bit 3 indicates the state of the interrupt pending (ip) latch. a 0 indicates that an interrupt is pending (the dma has its int line active if the interrupt has not been acknowledged). a 1 indicates no interrupt pending. bit 4 a 0 indicates that a match has been found after the last reset or reinitialize status byte command. a1 indicates no match was found. see table 11 to determine where the match occurred. bit 5 a 0 indicates that an end-of-block was reached after the last reset, load, continue, or reinitialize status byte command. a 1 indicates no end-of-block was reached. see table 12 to determine the contents of counters when the dma stops. bit 6 undefined. bit 7 undefined.

um008101-0601 direct memory access figure 47. read register 0 through read register 6 byte counter (rr1, rr2) this 16-bit counter is cleared to 0 by the load, continue, and reset commands only. when the dma begins transferring or searching, the byte counter increments by one at the end of each read cycle and the byte counter is compared with the programmed contents of the block length register, determining end-of-block. the number of bytes read in a transfer always equals the number of bytes written because the dma completes any transfer it starts, even when stopping on byte matches in transfer/search operations. d7 d6 d5 d4 d3 d2 d1 d0 status byte xx 1 = dma operation has occurred 0 = ready active 0 = interrupt pending 0 = match found 0 = end-of-block byte counter (low byte) read register 1 byte counter (high byte) read register 2 port a address counter (low byte) read register 3 port a address counter (high byte) read register 4 port b address counter (low byte) read register 5 port b address counter (high byte) read register 6

um008101-0601 direct memory access table 11 and table 12 illustrate how the pipelining of data affects the number of bytes transferred or searched in the various classes, modes, and circumstances of operation. in most cases, the number of bytes transferred in a transfer operation that stops at end-of-block is one more than the programmed block length. when the pulse-generation feature is used, the contents of the pulse control byte in wr4 are compared with the lower byte of the byte counter after each byte is transferred. port a address counter (rr3, rr4) this 16-bit counter is loaded from the port a starting address register in wr0 by the load command. it increments, decrements, or remains fixed according to the specifications in wr1. table 11 and table 12 show how this counter reads under various transfer or search conditions. port b address counter (rr5, rr6) this counter is identical to the port a address counter just described. if either port a or port b is a fixed-address destination port, it must be programmed as described in ?fixed-address destination ports? on page 121 to function properly. review of programming sequences this section describes programming the dma in both the general and in application-specific cases. also, see table 16 on page 127 for a sample dma program. dma initialization program all registers to be used in the dma at power-up. none of these registers contain useful defaults. this procedure includes the enabling of

um008101-0601 direct memory access interrupts and reinitialization of the status byte as well as many other func- tions, including class and mode designation, port designation, address and block-length designation. table 15 lists the order in which control bytes must be written for the initialization or reinitialization because of program abort. some of these control bytes may not be relevant to a specific application. all commands referred to are wr6 control bytes. thirty-five control bytes occur when all of the control bytes are written. all control bytes written to the dma disable the dma, except the enable dma command and possibly also the reinitialize status byte command and the wr0 control byte (when changing transfer direc- tions). the enable dma command must always be the last command written after any communication between the cpu and dma if the dma is to continue operating. furthermore, communication with the dma can only occur when the cpu is bus master. table 15. control byte order initialization/reinitialization sequence maximum number of z80 cpu bytes disable dma command 1 reset command (multiple) 6 wr0 control bytes 5 wr1 control bytes 2 wr2 control bytes 2 wr3 control bytes 3 wr4 control bytes 5 wr5 control bytes 1 resetportatimingcommand 1 resetportbtimingcommand 1 load command 1

um008101-0601 direct memory access port designation either port a or port b can be selected as the source or destination, (illus- trated in figure 19) because both ports feature the same degree of program- mability. when the destination port is also a fixed-address port, see the section ?fixed-address destination ports.? port characteristics are spec- ified in the following control byte groups: in a transfer, if the direction of transfer (bit 2 of wr0) changes, the wr0 control byte must be preceded by a different control byte, thereby insuring that the dma is disabled. reinitialize status byte command 1 read mask follows command 1 read mask control byte 1 initiate read sequence command 1 force ready command 1 enable interrupts command 1 enable dma command 1 total 35 port a port b wr0 wr0 wr1 wr2 wr6 wr4 wr6 table 15. control byte order (continued) initialization/reinitialization sequence maximum number of z80 cpu bytes

um008101-0601 direct memory access address loading write starting addresses to the starting-address registers for each port using wr0 (port a) and wr4 (port b). they are loaded to the address counters by the load command. the addresses must he written to the registers before they are loaded to the counters. new addresses may be written to the address registers at any time when the cpu is bus master, even between transfers and even when the dma is oper- ating in the auto restart mode, for example, in byte mode between byte transfers. with the exception of the auto restart mode, the new addresses must be reloaded before they are used. if a forced-ready condition is used, the load command must precede the force ready command. fixed-address destination ports a special circumstance arises when programming a destination port to have a fixed address. the load command in wr6 only loads a fixed address to a port selected as the source, not to a port selected as the destination. therefore, a fixed-destination address must be loaded after temporarily declaring its port as a source port. the true source port is subsequently declared (making the other port a destination) and the true source address is then loaded. the following example describes the steps in this procedure, assuming that transfers are to occur from a variable-address source (port a) to a fixed- address destination (port b). 1. write port b (fixed destination) address to wr4. 2. temporarily declare port b as source in wr0 (bit 2 = 0). 3. load port b address with the load command. 4. write port a (variable source) starting address to wr0. 5. declare port a as source in wr0 (bit 2 = 1). 6. load port a address with the load command.

um008101-0601 direct memory access 7. enable dma with the enable dma command. interrupts the interrupt vector (wr4) must be written before interrupts using it can occur, and interrupts must be enabled with the enable interrupts command at initialization or reinitialization. in a z80 cpu environment, interrupt service routines after dma initialization usually include the following commands at the end of the routine: 1. interrupt on end-of-block or byte match 2. enable dma command 3. reti instruction 4. interrupt on ready (before requesting the bus)

um008101-0601 direct memory access 5. enable after reti command 6. enable dma command 7. reti instruction interrupts at end-of-block, for example, might occur when reading a floppy disk. if the disk transfers 128-byte records, the dma can be made to interrupt at the end of each record to notify the cpu of its completion. then the cpu can read the destination (memory) address counter to find the last memory location filled. see table 12 for address-counter contents. a service routine for continuing inputs to contiguous locations of memory typically contains the continue , reinitialize status byte ,and enable dma commands before the cpu?s return from interrupt. a service routine for shutting down the dma after the record arrives typically includes disable dma and reinitialize status byte commands. if the dma transfer is started by an interrupt from another device, the service routine for that other device includes an enable dma command written to the dma?s port address. interrupts on byte match (a search or transfer/search operation) can be implemented so that any ending byte, error indicator, or other character causes the interrupt. this procedure frees the cpu from looking for these characters in a stream of data, increases throughput, and reduces cpu software complexity. for example, the dma might search for end-of-text (ext) characters or carriage returns in a communications environment and interrupt the cpu only when the complete message frame has arrived. the service routines for this would be very much like those for interrupts on end-of-block. interrupts on ready are somewhat different. first, the dma cannot be the bus master before the interrupt because the cpu only senses interrupts when the cpu is the bus master (the other types of interrupts are not

um008101-0601 direct memory access processed until the bus is released). second, to enable the dma, the enable after reti command must be used in the service routine after an interrupt on ready. the typical purpose of interrupting when the ready line comes active is to allow the cpu time to determine where a transfer should go, which it does in the service routine. this often occurs in systems with dynamic memory allocation and it improves the efficiency with which memory can be allocated. for example, the cpu might write and load new starting addresses for a memory destination to the dma in the service routine. only at the end of the service routine is the dma enabled to request the bus. the enable after reti command, which must precede the enable dma command, resets a latch that is set when the interrupt on ready first occurred. for non-z80 cpu environments, the disable interrupts , enable interrupts ,and reset and disable interrupts commands are available. they can simulate the z80 cpu?s interrupt-acknowledge cycle and return-from-interrupt instruction, both of which the dma needs to perform and return from interrupts. byte matching (searches) in stopping, or stopping and interrupting on match (wr3, wr4), to perform additional operations with the dma, the following sequence of commands are written: 1. load or continue. 2. reinitialize status byte. 3. enable dma. another command (with the exception of enable dma ) must precede the reinitialize status byte command. table 11 on page 76 describes the contents of various counters when stopping on byte match.

um008101-0601 direct memory access end-of-block after a stop or stop and interrupt on end-of-block (wr4 or wr5), where it is necessary to perform additional operations with the dma, write the same sequence of commands listed immediately under ?byte matching (searches)? on page 124. table 12 on page 76 describes the contents of various counters when stopping on end-of-block. auto restart to obtain a repetitive transfer or search using the same block length and starting addresses originally entered, initialize the dma including wr% bit 5 = 1. loading of addresses and clearing of the byte counter is auto- matic. when in byte mode (or burst mode where the ready line is occasionally released), it is possible to alter the starting addresses during a transfer (for example, between bus requests) without disturbing that transfer. at the end of this transfer, the dma automatically loads the new addresses to the counter and continues without interruption. force ready condition the force ready command is provided for operations such as memory-to- memory transfer or memory search-only where no ready line from an i/o device is used. however, several dma commands unforce the ready condition after the force ready command is written. the sequence of command entry is therefore important. this sequence is described in the force ready command in ?write register 6 group? on page 105. pulse generation to obtain pulses at 256-byte intervals, after a variable offset period, consider only the wr4 group. the int line is used for these pulses.

um008101-0601 direct memory access variable timing the timing on the rd ,wr ,mreq ,andiorq lines can be varied indepen- dently for either port by programming the wr1 and/or wr2 register groups. when programming memory-to-i/o, i/o-to-memory, or i/o-to-i/o sequential transfers or transfer/searches, the iorq line must be programmed in a specific way. see ?variable cycle (port a)? on page 96. enabling the dma the last command written to the dma before an operation occurs must be the enable dma command, or wr3 bit 6 = 1, which is equivalent. only this command makes the dma operate. if all other conditions for operation are satisfied at the time of enabling (for example, the ready line is active) the dma begins immediately. in an interrupt service routine, the enable dma command must be the last dma command written before the return from-interrupt instruction. other instructions usually follow the enable dma command in the service routine before the reti instruction is executed, but none of these commands affect the dma. reading status these two commands allow the cpu to read dma status: read status byte causes the next cpu read of the dma to access the status byte. every time the status byte is to be read, the read status byte command must first be written. initiate read sequence causes the next cpu read of the dma to access the first status register specified as readable by the read mask. subsequent reads of the dma, which must complete the sequence of all designated readable registers, do not require write commands. reading of the sequence of registers must be

um008101-0601 direct memory access completed before the next read status byte or initiate read sequence command. table 16 illustrates a program to transfer data from memory (port a) to a peripheral device (port b). in this example, the port a memory starting address is 1050h and the port b peripheral fixed address is 05h .the number of data bytes to be transferred is 1001h bytes (one more than spec- ified by the block length). the table of dma commands may be stored in consecutive memory locations and transferred to the dma with an output instruction such as the z80 cpu?s otir instruction. table 16. sample dma program d7 d5 d4 d3 d2 d1 d0 hex wr0 sets dma to receive block length, port a starting address, and temporarily sets port b as source. 01 block length upper follows 1 block length upper follows 1 port a upper address follows 1 port a upper address follows 0 b a tempor ary for leading b address 0 transfer. no search port a address (lower) 01 0 1 0 0 0 0 50 port a address (upper) 00 0 1 0 0 0 0 10 block length (lower) 0 0 0 0 0 0 0 0 00 block length (upper) 0 0 0 1 0 0 0 0 10 wr1 defines port a as memory with fixed incrementing address 00 no timing follows 0 address change s 1 address change s 0 port is memor y 10014 wr4 defines port a as memory with fixed incrementing address 00 no timing follows 1 fixed address 01 port is i/o 01028

um008101-0601 direct memory access wr4 sets mode to burst and sets dma to expect port b address 11 0 0 no interrup t control byte follows 0 no upper address 1 port b lower address follows 01c5 port b address (lower) 00 0 0 0 1 0 1 05 wr5 sets ready active high 10 0 no auto restart 0 no wait status 1 rdy active high 0108a wr6 loads port b address and resets block counter * 11 0 0 1 1 1 1 cf wr0 sets port a as source * 00 0 0 0 1 b a 0105 no address or block length bytes transfer no search wr6 loads port a address and resets block counter 11 0 0 1 1 1 1 cf wr6 enables dma to start operation. 10 0 0 0 1 1 1 87 table 16. sample dma program (continued) d7 d5 d4 d3 d2 d1 d0 hex

um008101-0601 direct memory access note: the actual number of bytes transferred is one more than specified by the block length. * these entries are necessary only in the case of a fixed destination address. z80 dma and cpu as a member of the z80 family, the z80 dma?s signals and timing are compatible with those of the z80 cpu. as bus master, the dma has read- and write-cycle characteristics identical to those of the z80 cpu, thereby simplifying system design. in addition, variable timing features allow the system designer to interface memories and i/o devices more easily with non-standard capabilities or requirements. the dma can shorten its read- or write-cycle timings for higher performance or lengthen and tailor control signals to accommodate slower devices. because these features are under programmed control, the hardware configuration is not affected by changes in cycle and control signal timings. interconnection in small systems, or where the z80 dma shares a board with the cpu, most of the pins on the dma may be connected directly to the corre- sponding cpu pins. these pins include the address bus (a15-a0), the data bus (d7-d0), and the control signals mreq ,iorq ,rd ,andwr .the interrupt request and bus request signals, int and busreq, may also be connected directly to the cpu, in common with corresponding open-drain outputs from other devices. the priority daisy-chains for these functions are described in an earlier chapter and are illustrated in figure 31 and figure 37. power, ground, and clock signals are also common to the cpu and dma, but extra care must be taken to provide low impedance paths and adequate decoupling. a 300 ohms pull-up from a ttl clock driver output may be adequate for small systems operating at the 2.5 mhz rate, but the increased loadings and speeds in larger high-performance systems require active pull-

um008101-0601 direct memory access up. a complementary-transistor driver for z80/z8000 systems is depicted in figure 48. chip selection and enabling z80 peripherals are normally addressed in the 256 address i/o space. each peripheral chip is enabled by an active-low chip enable (ce ) input. the ce input becomes active when an active iorq signal coincides with the peripheral?s address on the low order byte of the address bus. small systems may dedicate address lines to their few peripherals, making decoder hardware unnecessary. a system using dma, however, usually has more peripherals, so that address decoding by means of prom or msi ttl decoder is normally provided. figure 48. z80/z8000 clock driver figure 49 illustrates three chip enable arrangements in a small system. in it, the dma responds to half of the 256 possible i/o addresses. in (figure 49b), a 256 x 4 prom is programmed to provide a low output on the 01 pin only when the dma?s address is present. the prom must respond quickly to meet the dma?s ce setup time requirement. +5v ttl 0.01 f 10k (max) clock 2n5772 or 2n3646 120 470 470 240 22 22 2n5771 or 2n3546

um008101-0601 direct memory access figure 49c depicts a one-of-eight ttl decoder which provides chip enable signals for eight different peripheral devices. address bits a0 and a1 are often used directly by peripherals such as the z80 sio, pio, and ctc, and so are not decoded here. additional decoders can be added when more peripheral devices are present. iorq and m1 are internally gated with ce in z80 peripheral devices and need not be terms in ce. however, gating chip-enable signals with these control lines do no harm and may produce less-ambiguous logic sequences for circuit-level debugging, as seen in figure 49c.

um008101-0601 direct memory access figure 49. chip enable decoding with z80 cpu use of wait input when the dma is bus master, the ce /wait pin functions as an input from memory or i/o logic that may extend read or write cycles by requesting waits states. an active busack output from the cpu signals that the z80 cpu m1 iorq cpu m1 iorq dma m1 iorq ce dma m1 iorq ce ce7 ce1 a2 a3 a4 ce3 ce2 ce1 a5 a0 a7 a7 a0 a dma responds to i/o addresses 00h through 77h b prom determines dma response c dma responds to i/o addresses e0h through e3h dma m1 iorq ce address bus a7 a7 a0 04 03 02 01 256x4 prom cpu m1 iorq 1234567 0 74ls138 s0 s1 s2 e e e . . . .

um008101-0601 direct memory access cpu has relinquished the bus. therefore, if this dma is bus master, it samples the wait signal for these requests. a simple 2-input multiplexer steers the ce /wait signalsasdepictedinfigure50.usingbusack assumes that there is only one dma. in systems with three or more possible bus masters, bal active and bao inactive identify the master. simultaneous transfers the highest-speed dma transfer method is the simultaneous transfer method, or flyby method. this requires some external hardware to generate simultaneous read- and write-control signals to the source and destination ports. because the address bus is used for memory address, only transfers between i/o and memory can be accomplished directly when the i/o port selection is performed by hard wiring. the dma is put into search mode, and a circuit, such as that illustrated in figure 51, generates separate simul- taneous read- and write-control signals, which may be ored into the read- and write-control paths at memory and i/o. figure 52 depicts such an arrangement. this arrangement allows both the cpu and dma access to the i/o peripheral. (if the peripheral communicates only through dma, it only needs to use the iord and iowr signals.) pay careful attention to access, setup, and hold times in this mode. because the dma is programmed to do searching, the mwr and iowr signals are derived from the dma rd signal and mimic its timing. this does not cause a problem for write operations, which are trailing edge activated. to make mwr appear more like a cpu or dma write cycle signal, the circuit of figure 50 may be used to delay the leading edge of mwr until after the falling edge in t2. the programmable variable timing features of the dma may be useful, too.

um008101-0601 direct memory access figure 50. ce /wait multiplexer figure 51. simultaneous transfer multiplexer i1 i0 sel 1/4 74ls157 y dma ce /wait busack ce (from decoder) wait (from peripheral or memory logic) +5v iowr iord mwr mrd busack or bai -bao rd (from dma) iorq (from dma) y4 y3 y1 sel 74ls257 oe y2 01000 111

um008101-0601 direct memory access figure 52. simultaneous transfer dma iorq rd wr busack bai rd iorq mrd mwr high rd wr memory i/o dma i/o decoder ioce iowr iord address and data buses rd wr ce oe y1 y2 y3 y4 sel 1 000 11 0 1

um008101-0601 direct memory access figure 53. delaying the leading edge of mwr bus buffering microcomputer systems using dma often include large memories, many peripheral devices, or occupy several circuit cards. in these cases, the system buses and control signals require buffering to increase drive capa- bility and noise margin and to decrease delay times. the need for buffering within a single circuit card can be estimated by comparing drive capabilities of bus master devices (cpu and dma) to loadings presented by all inputs and outputs connected to the buses. both static (dc current) and dynamic (capacitive drive) requirements must be considered. when driving a motherboard or other cards, buffering is a prac- tical necessity. if the bus master devices (cpu and dmas) are on the same card, they can share buffers for address, data, and control buses to other cards. otherwise, each card?s bus interfaces require buffering. address lines are unidirectional and can be buffered by many common devices such as 74ls244 and 74ls367 (non-inverting tristate buffer/ drivers) or 74ls240 and 74ls366 (inverting tristate buffer/drivers). the tristate enable inputs on buffers such as these allow the bus to be isolated +5v clk busack dmwr mwr clk pre d q 1/2 74ls74

um008101-0601 direct memory access (floated) in a manner similar to the cpu and dma address pins. for example, in a system with one cpu and one dma, the busack signal can disable cpu buffers and enable dma buffers when it is active. where there are three or more potential bus masters, only those buffers associated with the actual bus master must be active at any time. therefore, each dma, if its bai signal is active (low) and its bao signal is inactive (high), has control of the bus and can enable its drivers. data bus lines are bidirectional, making their buffer control more compli- cated. any device from which the cpu can read drives the data bus when it is selected and the rd control signal is active. in this sense, the rd signal is the principal directional control. non-cpu devices also drive the data bus during interrupt-acknowledge cycles in which the device puts its vector on the bus and during dma write cycles. figure 54 illustrates a bidirectional data bus buffer and its control. here, z80 sic, pio, ctc, and dma peripherals share a circuit card. their common on-card data bus is buffered to and from the system (motherboard or backplane) bus. each of the three conditions mentioned causes the buffers to drive data out onto the system bus; otherwise, data is buffered into the card. suitable devices for bidirectional buffering include the 74ls241 (tristate bus drivers) and 74ls245 (transceivers). the control signals mreq ,iorq ,rd ,andwr should be unidirectionally buffered in large- or multi-card systems. these signal buffers are, again, enabled when their associated device or card has bus control and are forced into high-impedance states when another master takes control of these bus lines. because there are short intervals during transfer of the bus (when the bus is not driven by any master), mreq ,iorq ,rd ,andwr should be pulled up to + 5v with 2.7 kohms to 4.7 kohms resistors so that they remain inactive. other control signals on cpu and dma may be perma- nently driven. this usually includes m1 , rfsh ,andhalt from the cpu, and bao from a dma. the busreq line is bidirectional and cannot easily be externally buffered. however, the dma can sink 3.2 ma on busreq ,morethanonother

um008101-0601 direct memory access signals. to maximize current, the system?s busreq pull-up resistor can be as low as 1.8 kohms. ttl buffers and drive capacitive loads while the dc output ratings of standard buffers such as the 74ls367 are usually ample, propagation times through these buffers are rated at capac- itive loadings of only 30 pf, a value easily exceeded in practice. capacitive loading thus usually dominates bus driving requirements. z80 family parts are specified over ranges of capacitive loading. the load seen by a device driving a bus line has components due to wiring and printed circuit land capacitance, connector capacitance, and capaci- tances of inputs and outputs connected to the signal. a standard low-power schottky (ls) ttl input presents about 6 pf of capacitive load, an ls output of about 8 pf. most other input and output capacitances can be esti- mated from device data sheets, but capacitance associated with intercon- nection may vary markedly. sometimes, propagation delays and allowable capacitive loading for buffered lines must be determined by measurement or by trial and error.

um008101-0601 direct memory access figure 54. data bus buffer control example z80 dma and z80 sio example a common dma application is performing data transfers over a serial data link. the z80 sio peripheral is used to interface to the link, providing conversion between serial and parallel data formats, synchronization, and other functions. comparing the efficiency of interrupt driven and dma data transfers requires examination of the event sequences during the brief time intervals in which the sio needs a character (byte) transfer. most of the time the sio is busy transmitting or receiving message bits and requires no service. the sio must be programmed to drive its wait /rdy line as a rdy signal to the dma, which is programmed for active-low rdy in byte mode. on .card .int ack rd dma .write on .card .read on .card .enable dir en drive .data .out on-card data bus system data bus 47ls 245 rd card.ieo card.iei m1 iorq dma .ce sio .ce pio .ce ctc .ce dma .has .bus

um008101-0601 direct memory access the event sequences for sio-dma transfers are described in table 17 and table 18. table 17. receive event sequence event inter-event delay (clock periods) sio receives last bit of character 10-13 latency sio rdy becomes active 2 latency dma asserts busreq 1-5 latency current cpu machine cycle ends 1 latency, bus occupancy cpu asserts busack 4 latency, bus occupancy dma i/o read cycle begins 4 latency, bus occupancy dma memory write cycle begins 2 bus occupancy dma terminates busreq 1 bus occupancy dma memory write cycle ends 1 bus occupancy cpu terminates busack and regains control of bus 1 bus occupancy note: latency (delay from reception of final data bit to reading of received data) is 22 to 29 clock periods. the system bus is occupied by the dma for 13 clock periods per byte transferred. table 18. transmit event sequence event inter-event delay (clock periods) sio transmits last bit of character 5-6 latency sio rdy becomes true 2 latency dma asserts busreq 1-5 latency current cpu machine cycle ends 1 latency, bus occupancy cpu asserts busack 4 latency, bus occupancy dma memory read cycle begins 3 latency, bus occupancy

um008101-0601 direct memory access in an interrupt-driven cpu transfer scheme, the sio must interrupt the cpu whenever it has received a character or needs another character to transmit. a very short benchmark service routine, which assumes the exclusive use of the z80 cpu?s alternate register set for sio interrupt handling, is provided below.the numbers in parentheses are clock periods per instruction. before the service routine can be executed, the cpu must have its inter- rupts enabled, finish its current instruction, and execute an interrupt acknowledge cycle (19 clock periods). this optimistic benchmark takes at least 68 clock periods per byte transferred, and severely restricts cpu activity by permanently occupying the alternate register set. to compare these transfer methods, the ratios of clock cycles used per kbaud to clock cycles available per second can be calculated. these dma i/o write cycle begins 3 latency, bus occupancy dma terminates busreq 1 latency, bus occupancy dma i/o write cycle ends 1 latency, bus occupancy cpu terminates busack and regains control of bus 1 bus occupancy siosvc: exx ; get transfer parameters (4) outi ; transfer a byte, ; update parameters (16) jrz,blkend ; test for end-of-block (7) exx ; save parameters (4) ei ; reenable interrupts (4) reti (14) table 18. transmit event sequence (continued) event inter-event delay (clock periods)

um008101-0601 direct memory access represent the fractional reductions in cpu throughput per kbaud trans- ferred. the dma has a shorter and more predictable latency period and decreases system overhead by at least a factor of five in this conservative example. a diagram of a typical z80 system using a z80 cpu, a z80 ctc for asyn- chronous baud rate generation, both channels of a z80 sio, and two z80 dmas (one for each serial channel) appears in figure 55. the diagram omits the system memory (rom and ram), bus buffers (as required), and chip enable decoders, which are described above. z80 (2.5 mhz) Z80A (4 mhz) dma sequential transfer 0.065% 0.041% dma sequential transfer/search interrupt-driven transfer 0.340% 0.213%

um008101-0601 direct memory access figure 55. dma-sio environment using the z80 dma with other processors the z80 dma offers great versatility and is a powerful alternative for board designers. because the dma is designed as a member of the z80 family, it requires certain signals and bus characteristics, such as those of +5v +5v sio rxca w /rdya w /rdyb rxcb txca txcb cpu dma dma int int int iei rdy ieo iei rdy s ystem buses common: a16?a0 d7?d0 clk int busreq m1 iorq mreq rd wr iei zc/to1 zc/to2 ieo ctc int

um008101-0601 direct memory access the z80 bus, to function. these functions are described in the following sections, and design solutions are offered: bus request/release mechanisms bus characteristics interrupt request, acknowledge, and return bus request/release mechanisms the most fundamental characteristic that distinguishes the z80 dma from other monolithic dmacs is its full control of the system bus during its active state. therefore, processors using the dma must be able to give up control of the system bus, including address, data, and the control lines mreq ,iorq ,rd ,andwr (or their equivalents). some processors have no mechanism for freeing the bus. others, including the 6800, have rudi- mentary bus control facilities, but because of their internal dynamic logic implementations, cannot relinquish control for indefinite periods of time. this makes them difficult to interface to the dma. many popular microprocessor cpus, however, do have adequate bus control facilities, and some are very similar to the z80 busreq and busack signals. for instance, the 8080, 8085, and 8086 signals hold and hlda are very close approximations. the active levels of hold and hlda are positive rather than negative, and variations exist in timing. but the use of hold and hlda allows the address and data bus drivers to be put into their high-impedance states. in 8080 systems using an 8238 to demultiplex commands, the memw , memr ,iow, and ior control lines can be floated using the busen input. with the 8085, a tristate decoder allows decode or disable corre- sponding signals. the 8086 and its support chips also tristate their control signals when hlda is active.

um008101-0601 direct memory access bus characteristics similar to the z80, the 8080 and 8085 have 8-bit data paths and 16-bit addresses. the dma is matched well to these numbers; it can search whole data words and directly address any byte in the memory. the 8086 and the z8000 cpus have 16-bit data paths and larger address spaces, thus making it somewhat harder to use the z80 dma. searching can be done for match bytes in either half of the data word, but not for a whole unique word. often this is not a problem because byte matches suffice, for example, in detecting special ascii characters in a data block. the problem of larger address spaces can be resolved by using an external segment or page register, latched to the appropriate high-order addresses before the dma becomes bus master, or by other schemes such as indexing. this requires some external hardware. to conserve pins, the 8085, 8086, z8001, and z8002 multiplex addresses and data. strobes allowing demultiplexing then become part of the bus structure and must be accounted for in dma interface. in such cases, the dma should be connected to the demultiplexed address and data lines rather than closer to the processor. figure 56 is a simplified diagram of this concept.

um008101-0601 direct memory access figure 56. connecting dma to demultiplexed address/data buses many processors encode their control signals, as does the z80?s m1 , mreq ,iorq ,rd ,andwr , into status words that are often demultiplexed before they are distributed to memory, peripherals, and more. link the dma to these demultiplexed signals and take advantage of tristate decoders to float the outputs when the dma is master. the dma?s z80-like control signals must usually be retimed to meet the requirements of the foreign buses. but the programmable timing feature of the dma may well reduce the hardware costs incurred. interrupt request, acknowledge, and return when using the dma with other processors, this area is the most chal- lenging because of the many methods of signaling, prioritizing, identifying, responding to, and returning from interrupts. latched address bus cpu dma buffered bidirectional data bus multiplexed address and data bus 3-stage latches

um008101-0601 direct memory access non-z80 interrupt environments do not use the iei and ieo signals, and often they use separate interrupt controllers to generate vectors, and handle acknowledgement and return in different ways, or not at all. interrupt request is usually easy: active levels typically are low voltage, and there may be one or more separate interrupt request pins. timing require- ments for interrupt requests are varied and may including pulse widths, latching, and more, and must be carefully examined. priority of simultaneous or overlapping requests is handled in several ways: some processors (for example, the 8085) have multiple interrupt-request pins, some use daisy-chained priority schemes (as in the z80), and several types of interrupt control ics are available. acknowledgement and identification methods vary too. sometimes, several fixed memory locations correspond to different interrupt pins? service routines. in other cases, the interrupting device identifies itself by putting a vector or instruction on the data bus for the cpu to read. interrupt controllers often provide appropriate vectors to the cpu and distinguish between and prioritize multiple requests. the dma has the built-in capa- bility of supplying an arbitrary vector byte when it detects a z80 interrupt acknowledge (iorq and m1 both active) and its iei input is active (no higher-priority device is interrupting). often, then, gating the m1 ,iorq , and iei pins appropriately can rule out using a separate interrupt controller. iorq serves another function, too, therefore it must appear during cpu- dma transfers and be available to signal i/o reads or writes in the active state. at the end of its service routine, the dma anticipates the cpu fetching the reti instruction (ed, 4d present on the data bus accompanied by m1) . the dma command reset and disable interrupts is designed for this purpose in non-z80 cpu environments. alternatively, the reti instructionmightbesimulatedbyre-gatingm1 and programming the cpu to write to a phantom peripheral the bytes ed, 4d. the chip select for this nonexistent peripheral is used to simulate m1. seefigure57.

um008101-0601 direct memory access figure 57. z8000/z80 peripheral interface +5v clr clk ls74 dq pre q ls32 ls10 ls10 ls32 ls04 y0 y1 y2 y3 y4 y5 reti g1 g2a g2b c b a ls138 +5v iorq ls06 to z 80 peripherals ce0 ce1 ce2 ce3 +5v iorq clock r/w viack (vectored interrupt acknowledge from st3-st0) ds as la5 la4 la3 from z8000 data bus ls08 rd ls06 iorq pre clr clk ls74 d q q

um008101-0601 direct memory access performance limitations bus contention using the direct memory access (dma) as bus master can negatively effect cpu activity by preventing the cpu from fetching and executing instructions. this method of bringing the cpu to a halt creates problems, including: no interrupt servicing (including nonmaskable cpu interrupts) no refresh of dynamic memory (if performed by the cpu) no polling the cpu?s time-critical functions are affected by which operating mode the dma is using. these modes are byte, burst, and continuous. byte mode when bus contention occurs, using byte mode allows interleaving of cpu functions and dma functions for each byte of data transferred. the disadvantage to using this mode is slower transfer speed. burst mode burst mode is useful when transferring data in short segments over a longer period of time. this mode has the advantage of using the bus only when needed. during those times, transfer speeds are maximized. however, this mode may not be suitable for extended bursts of data (long periods when the ready line is active). burst mode allows the dma to release the bus back to the cpu before other cpu-dependent functions are compromised.

um008101-0601 direct memory access continuous mode continuous mode monopolizes the bus until the end-of-block or byte match is reached, regardless of the state of the ready line. while achieving the fastest transfer speeds, this mode is employed when no time-critical functions are dependent upon the cpu or when the data blocks are relatively short. byte mode is used for most applications. when considering the use of burst or continuous modes, the following must be known: maximum block length maximum dma transfer rate (see table 8) maximum time ready line remains active the dma can be forced off the bus in either byte or burst mode. figure 58 illustrates how an external gate is used to remove the rdy- input state from the dma. forcing the dma to stop in the middle of a transfer cannot be used when the dma is operating in continuous mode. only a power-down or normal termination with end-of-block or byte match can make the dma release the bus. figure 58. dma bus-master gate (byte or burst modes only) control overhead the cpu becomes less efficient when the dma?s software must be initialized or updated. as table 15 illustrates, thirty-five control bytes are required to initialize a fully functioning dma. in addition, using the interrupt mode requires servicing by the cpu, which demands writing additional control bytes to the dma. user supplied rdy to dma force.off.bus

um008101-0601 direct memory access system throughput is decreased for applications requiring frequent dma reprogramming or extensive interrupt service of data-independent dma functions. it is more efficient to transfer large blocks of repetitive data. timing the cpu as bus master when the cpu is the bus master, control bytes can program the direct memory access (dma). writing control bytes table 13 illustrates the disabled, enabled/inactive, or enabled/stopped states. the enabled/inactive and enabled/stopped states are equivalent. the dma is programmed by being addressed as an i/o peripheral in a cpu output instruction. the dma can be addressed in the full 64k i/o space. to accomplish this, three lines must be simultaneously active-low on the ris- ing edge of the clock: ce chip enable iorq input/output request wr write figure 59 illustrates the timing required for this process. in a z80 cpu environment, this timing occurs automatically when the cpu and dma are on the same board and have no buffers, drivers, or other external gates in series with the common cpu and dma pins. this timing applies to the sequential transfer, sequential transfer/search, and search-only classes of operation. it may or may not apply to the simultaneous transfer or simulta- neous transfer/search operations, depending on the speed of the external devices used (see the applications chapter).

um008101-0601 direct memory access figure 59. cpu-to-dma write cycle requirements to write to the dma control bites, the following conditions must be met: the dma?s ce line must be low (normally done by decoding the lower byte of the address bus). the iorq and wr lines must be low at this time. the control byte must be placed on the data bus so that it is stabilized at a rising clock edge, which occurs one clock period after the ce , iorq ,andwr lines have stabilized. reading status bytes figure 60 illustrates the timing needed for the cpu to read the dma?s read registers, rr6 through rr0, while the cpu is bus master. to read a regis- ter, this condition must be met: the ce ,iorq ,andrd lines must be active and stabilized over two rising edges of the clock. status data becomes available on the data bus at the time of the second clock rising edge, which remains on the bus for as long as both the ce , iorq ,andrd lines remain active. clk ce iorq wr d7?d0

um008101-0601 direct memory access figure 60. cpu-to-dma read cycle requirements the dma as bus master sequential transfers in sequential transfer and transfer/search operations, which both have the same timing, data is latched onto the bus by the rising edge of the rd sig- nal, with standard timing this is the falling edge of t3. data is held on the data bus across the boundary between read and write cycles, through the end of the following write cycle. the dma data bus drivers become active when rd becomes inactive. figure 61 illustrates the timing for memory-to-i/o port transfers, and figure 62 illustrates i/o-to-memory transfers. memory-to-memory and i/o to-i/o transfer timings are simply permutations of these diagrams. the default timing uses three clock cycles for memory transactions and four clock cycles for i/o transactions, which include one automatically inserted wait cycle between t2 and t3. if the ce /wait line is pro- grammedtoserveasawait line during the dma?s active state, it is sam- pled on the falling edge of t2 for memory transactions and the falling edge of tw for i/o transactions. if ce /wait is low during this time, another t- cycle is added, during which time the ce /wait line is again sampled. the duration of transactions can thus be indefinitely extended. clk ce iorq wr d7?d0

um008101-0601 direct memory access simultaneous transfers the timing for simultaneous transfers and simultaneous transfer/searches is the same. the dma is programmed in the search-only mode, and both read and write cycles occur simultaneously in the time that a source-port read would occur in search-only. only one address is generated on the address bus; the i/o port is hardwire-selected during this operation as shown in the applications chapter. the iorq ,mreq ,rd, and wr lines are gated into two new signals by external logic. these signals are either: memwr (memory write) iord (i/o read) or: memrd (memory read) iowr (i/o write)

um008101-0601 direct memory access figure 61.sequential memory-to-i/o transfer, standard timing (searching is optional) ce /wait d7?d0 memory drive dma dma drives data bus wr iorq rd mreq read write a15?a0 clk memory read i/o write t 1 t 2 t 3 t 2 t w t 3 t 1

um008101-0601 direct memory access figure 62. sequential i/o-to-memory transfer, standard timing (searching is optional) ce /wait i/o drives memory dma drives data bus wr iorq rd mreq read write a15?a0 clk i/o read memory write t 1 t 2 t w t 1 t 2 t 3 t 3 iorq

um008101-0601 direct memory access figure 63. simultaneous memory-to-i/o transfer (burst and continuous mode) ce /wait a15?a0 clk t 1 t 2 t 3 d7?d0 iowr memrd c ycle 1 c ycle 2 c ycle 3

um008101-0601 direct memory access figure 64. simultaneous memory-to-i/o transfer (byte mode) figure 63 illustrates the timing for simultaneous transfers in burst and con- tinuous modes between memory and i/o, using standard z80 timing. the timing within each cycle is similar to the memory read cycle shown in figure 61. the address bus activity is the same, and the cycle length is the same. however, the mreq ,rd ,iorq ,andwr lines in figure 61 have been changed to memrd and iowr lines in figure 63. in addition, the data bus becomes active earlier in figure 63, in response to the memrd line becoming active. data is clocked to the l/o port on the rising edge of iowr figure 64 depicts the timing for byte mode. timing is identical to figure 63 within each cycle. the breaks between each cycle, where the address and data bus are tristated and the memrd and iowr lines remain ce /wait a15?a0 clk d7?d0 iowr memrd c ycle 2 dma drives the last data it read during this time cycle 1

um008101-0601 direct memory access inactive, are caused by the activity on the busreq and bai lines, which is explained later. search-only the standard timing for search-only operations is identical to the read cycles of figure 61 and figure 62. search-only is equivalent to read-only. data is read to a dma register for comparison with the match byte. bus requests figure 65 illustrates the bus request and acceptance timing. the rdy line, which may be programmed active high or low, is sampled on every rising edge of clk. if the rdy line is active, and if the bus is not in use by any other device, the following rising edge of clk drives busreq low. after receiving bus- req the cpu acknowledges on its busack , which is connected to the dma?s bai input either directly or through a multiple-dma daisy-chain. the cpu checks its busreq input one clock cycle before the end of each cpu machine cycle. if the cpu detects a request, it releases the bus at the end of that same machine cycle. the maximum time delay between the cpu receiving busreq and the response on its busack line is one machine cycle plus slightly less than one clock cycle. the cpu tristates all its bus control lines when it acknowledges on the busack line. m1 is not tristated. the rdy line, which has a specified setup time with respect to a rising edge of clk, must remain active until after the dma becomes bus master in byte or burst modes.

um008101-0601 direct memory access figure 65. bus request and acceptance timing continuous mode is the only instance when a pulse on rdy allows the dma to become bus master.in this event, the dma becomes bus master but does not begin operations. when the dma detects a low on bai for two consecutive rising edges of clk, the dma begins transferring data on the next rising edge of clk. in byte mode, after each byte is transferred, the dma waits until its bai line goes inactive before requesting the bus again on busreq for the next byte transfer. this feature allows a minimum of one cpu machine cycle to occur between each byte transferred. bus release byte-at-a-time in byte mode, busreq is brought high on the rising edge of clk prior to the end of each read cycle (search-only) or write cycle (transfer and trans- fer/search) as illustrated in figure 66. this action occurs regardless of the state of rdy. there is no possibility of confusion when a z80 cpu is used because the cpu cannot begin an operation until the following clock cycle. nor does this condition affect most other cpus. the result of timing is one- clock-cycle less time needed for a byte transfer. busreq rdy active inactive dma inactive dma active bai clk note: rdy is detected as a level, not an edge

um008101-0601 direct memory access figure 66. bus release in byte mode the next bus request for the next byte comes after both busreq and bai have returned high. in a z80 environment, bai returns high one clock cycle after busreq returns high. bus release on end-of-block. when the dma is programmed to stop on end-of-block in burst or contin- uous modes, an end-of-block causes busreq to go high (inactive) on the same rising edge of clk in which the dma completes the data block transfer (see figure 67). the last byte in the block is transferred even if rdy goes inactive before completion of the last byte operation. figure 67. bus release on end-of-block (burst and continuous modes) busreq dma active bai clk dma inactive busreq rdy current byte operation dma inactive active inactive

um008101-0601 direct memory access bus release on match when the dma is programmed to stop (release the bus) on match in burst or continuous modes, a match causes busreq to go inactive on the next dma operation, for example, at the end of the next read in search-only, simultaneous transfer/searches, or at the end of the following write in sequential transfer or transfer/searches (figure 68). figure 68. bus release on match (burst and continuous modes) because of the pipelining scheme, matches are determined while the next dma read or write is being performed. table 12 lists the number of bytes transferred in any class or mode. the rdy line can go inactive after the matching operation begins without affecting this bus-release timing. however, the time at which rdy goes inactive can affect the number of bytes transferred, as described in table 11 and figure 32. bus release on not ready burst mode, when rdy goes inactive, causes busreq to go high on the next rising edge of clk after the completion of its current byte operation, for example, at the end of the current read in search-only, simultaneous transfer/search, or at the end of the following write in sequential transfer/ busreq rdy byte n dma inactive read in byte n+1 and on byte n read in match found active inactive clk

um008101-0601 direct memory access search (figure 69). the action on busreq is thus somewhat delayed from action on the rdy line. the dma always completes the current byte oper- ation in an orderly fashion before releasing the bus. figure 69. bus release on not ready (burst mode) by contrast, busreq is not released in continuous mode when rdy goes inactive. instead, the dma idles after completing the current byte opera- tion, awaiting an active rdy again. figure 70, figure 71, and figure 72 review the relationship between the ready line going inactive and the state of the other lines for each mode of operation, assuming a search-only of memory using standard z80 timing. the timing for ready coming active is discussed under bus request. rdy is sampled on the rising edge of clk in the last clock cycle of each read or write cycle. it is a level-sample, not an edge-sample. rdy can go inactive prior to the completion of the last byte operation without disturbing that operation. at the end of that operation, the busreq and bai lines go high in byte or burst mode according to figure 68 and figure 71. the bus control lines mreq ,iorq ,rd ,andwr, also remain high in byte and burst mode during an inactive rdy, with both the address and data buses tristated. the continuous mode (figure 72) is different because the address bus holds the pre incremented address for the next byte throughout the time that rdy is inactive. this address is immediately available when rdy comes active again. busreq rdy dma inactive active inactive clk current byte operation

um008101-0601 direct memory access figure 70. rdy line in byte mode a15?a0 d7?d0 rd mreq busreq bai rdy a ct i ve

um008101-0601 direct memory access figure 71. rdy line in burst mode a15?a0 d7?d0 rd mreq busreq bai rdy

um008101-0601 direct memory access figure 72. rdy line in continuous mode variable cycle and edge timing the z80 dma?s operation-cycle length, without wait states for the source (read) port and destination (write) port, can be independently programmed. this variable-cycle feature allows read or write cycles consisting of two, three, or four clock cycles, more if wait cycles are inserted, increasing or decreasing the pulse widths of all signals generated by the dma. in addi- tion, the trailing edges of the iorq ,mreq ,rd ,andwr signals can be independently terminated one-half cycle early. see figure 73 . a15?a0 d7?d0 rd mreq busreq bai rdy

um008101-0601 direct memory access figure 73. variable-cycle and edge timing in the variable-cycle mode, unlike default tuning, iorq comes active one- half cycle before mreq ,rd ,andwr .ce /wait can be used to extend only the 3 or 4 clock cycle variable memory cycles and only the 4-cycle variable i/o cycle (see figure 75). the ce /wait line is sampled at the falling edge of t2 for 3- or 4-cycle memory operations, and at the falling edge of t3 for 4-cycle i/o operations. the line is not sampled for 2-cycle operations. during transfers, data is latched on the clock edge, causing the rising edge of rd and held until the end of the write cycle. using variable timing on an i/o-search, a simultaneous transfer, or transfer/ search with i/o as the source port, creates a unique situation. in these appli- cations, the iorq line must be programmed to end early. see ?write regis- ter 1 group? on page 96. the simultaneous transfers are programmed in the dma as searches and are only distinguished from searches by the way external logic handles the bus control signals. figure 72 illustrates the bus control lines (mreq and rd) remaining inac- tive when the rdy line goes inactive in continuous mode. the same is not true of the iorq line when variable timing is used. in this instance, iorq clk iorq a15?a0 t 1 t 2 t 3 t 4 mreq rd ,wr 2-cycle early end 3-cycle early end 4-cycle early end

um008101-0601 direct memory access and any functions created from it by external logic in simultaneous transfer operations (such as iowr and iord), remain active during an inactive rdy line before stopping on end-of-block or byte match. interrupts timings for interrupt acknowledge and return from interrupt are the same as timings for these in other z80 peripherals. figure 74 illustrates this timing. the interrupt signal int issampledbythecpuontherisingedge of the final clock cycle of any instruction. the signal is not accepted if the internal cpu software-controlled interrupt-enable flip-flop is not set or if the busreq signal is active. when the int signal is accepted, a special m1 cycle is generated. figure 74. wait line sampling in variable-cycle timing during this special m1 cycle, the iorq signal becomes simultaneously active (instead of the normal mreq) , indicating that the interrupting device can place its 8-bit vector on the data bus. two wait states are auto- matically added to this cycle. these states are added so that a ripple-priority interrupt scheme can be easily implemented. the two wait states allow time for the ripple signals to stabilize and identify what i/o device must respond. refer to the z80 cpu user?s manual for more details. clk t 1 t 2 t 3 t 4 ce /wait (4-cycle i/o operations) ce /wait (3-cycle and 4-cycle memory operations)

um008101-0601 direct memory access interrupt on rdy (interrupt before requesting the bus) does not directly affect the busreq line. instead, the interrupt service routine may handle this by issuing the following commands to wr6: enable after return from interrupt (reti) command ? b7h an reti instruction that resets the interrupt under service (ius) latch in the z80 dma ? edh, 4dh. pulse generation when the pulse generation option is selected, the int line is driven low every 256 bytes after the offset value. the line goes low during the dma cycle in which the pulse-control byte matches the lower byte of the byte counter, and it remains low for one complete transfer cycle. a transfer cycle is defined as either a read cycle (search-only or simultaneous transfer operations) or a read plus a write cycle, where read and write cycles can be independently programmed for length through the variable-cycle option.

um008101-0601 direct memory access figure 75. interrupt acknowledge a7?a0 rd wait clock in int data bus m1 iorq mreq pc last m c ycle of instruction t 1 last t state m1 refresh t 2 t w t 3 t w

um008101-0601 direct memory access register bit functions write register bit functions figure 76. write register 0 group figure 77. write register 1 group d7 d6 d5 d4 d3 d2 d1 d0 base register byte port a starting address 00 0 1 1 1 0 1 do not use =transfer =search = search/transfer 0 =portb port a 0 =porta port b (low byte) port a starting address (high byte) block length (low byte) block length (high byte) d7 d6 d5 d4 d3 d2 d1 d0 base register byte 00 0 1 1 1 0 1 = port a address decrements 0 = port a is memory 0 = port a is i/o port a variable 00 0 1 1 1 0 1 = cycle length = 3 = cycle length = 2 =donotuse = port a address increments = port a address fixed timing byte = cycle length = 4 wr ends 1/2 cycle early = 0 rd ends 1/2 cycle early = 0 mreq ends 1/2 cycle early = 0 0 = iorq ends 1/2 cycle early 00 00 1 0

um008101-0601 direct memory access figure 78. write register 2 group figure 79. write register 3 group d7 d6 d5 d4 d3 d2 d1 d0 base register byte 00 0 1 1 1 0 1 = port b address decrements 0 = port b is memory 1 = port b is i/o port b variable 00 0 1 1 1 0 1 = cycle length = 3 = cycle length = 2 =donotuse = port b address increments = port b address fixed timing byte = cycle length = 4 wr ends 1/2 cycle early = 0 rd ends 1/2 cycle early = 0 mreq ends 1/2 cycle early = 0 0=iorq ends 1/2 cycle early 00 0 0 d7 d6 d5 d4 d3 d2 d1 d0 base register byte mask byte (0 = compare) 00 0 dma enable = 1 interrupt enable = 1 1=stoponmatch match byte

um008101-0601 direct memory access figure 80. write register 4 group d7 d6 d5 d4 d3 d2 d1 d0 base register byte 0 0 0 0 = interrupt on end-of-block = interrupt on match and = interrupt on rdy 01 1 port b starting address pulse control byte interrupt on rdy = 1 status affects vector = 1 1=pulsegenerated interrupt vector end-of-block 0 0 0 0 modified as shown only if ?status affects vector? vector is automatically bit is set 1 = interrupted at end-of-block 1 = interrupted on match 0 interrupt control byte (high byte) port b starting address (low byte) 0 1 0 1 0 0 1 1 continuous = burst = do not program = byte = = interrupt on match

um008101-0601 direct memory access figure 81. write register 5 group figure 82. write register 6 group d7 d6 d5 d4 d3 d2 d1 d0 base register byte 0 = ready active low 1 = ready active high 10 0 10 0 =stoponend-of-block 1 = auto restart on end-of-block 0 =ce only 1 =ce /wait multiplexed d7 d6 d5 d4 d3 d2 d1 d0 base register byte 0 1 11 1 =c3=reset 000 hex command name 0 1 =c7=resetportatiming 001 0 1 =c8=resetportbtiming 010 0 1 = cf = load 011 0 1 = d3 = continue 100 1 0 = af = disable interrupts 011 1 0 = ab = enable interrupts 010 1 0 = a3 = reset and disable interrupts 000 1 0 = b7 = enable after reti 101 1 0 = bf = read status byte 111 0 0 = 8b = reinitialize status byte 010 1 0 = a7 = initialize read sequence 001 1 0 =b3=forceready 100 0 0 = 87 = enable dma 001 0 0 =83=disabledma 000 1 0 = bb = read mask follows 110 base register byte status byte byte counter (low byte) byte counter (high byte) port a address (low byte) port b address (high byte) 0 port b address (low byte) port a address (high byte)

um008101-0601 direct memory access read register bit functions figure 83. read register 0 through 6 bit functions d7 d6 d5 d4 d3 d2 d1 d0 status byte xx 1 = dma operation has occurred 0 = ready active 0 = interrupt pending 0 = match found 0 = end-of-block byte counter (low byte) read register 1 byte counter (high byte) read register 2 port a address counter (low byte) read register 3 port a address counter (high byte) read register 4 port b address counter (low byte) read register 5 port b address counter (high byte) read register 6

um008101-0601 direct memory access

um008101-0601 parallel input/output parallel input/output overview the z80 parallel input/output (pio) circuit is a programmable, two-port device that provides a ttl-compatible interface between peripheral devices and the z80 cpu. the cpu configures the z80 pio to interface with a wide range of peripheral devices with no other external logic required. typical peripheral devices that are fully compatible with the z80 pio include most keyboards, paper tape readers and punches, printers, and prom programmers. the z80 pio package is available in 40-pin dip, 44- pin plcc, or 44-pin qfp. the cmos version is available in all three pack- age configurations. the nmos version is available in 40-pin dip and 44- pin plcc. one unique feature that separates the z80 pio from other interface control- lers is that all data transfers between the peripheral device and the cpu is under total interrupt control. the pio interrupt logic allows full use of the efficient interrupt capabilities of the z80 cpu during i/o transfers. all logic necessary to implement a fully nested interrupt structure is included in the pio, requiring no additional circuits. another unique feature is that the pio can be programmed to interrupt the cpu on the occurrence of speci- fied status conditions in the peripheral device. for example, the pio can be programmed to interrupt when any specified peripheral alarm conditions occur. this interrupt capability reduces the amount of time spent by the pro- cessor polling peripheral status. features two independent 8-bit bidirectional peripheral interface ports with handshake data transfer control interrupt-driven handshake for fast response

um008101-0601 parallel input/output four modes of port operation with interrupt-controlled handshake: ? byte output ? byte input ? byte bidirectional bus (available on port a only) ? bit control mode daisy-chain priority interrupt logic, allowing automatic interrupt vectoring without external logic eight outputs capable of driving darlington transistors fully ttl-compatible inputs and outputs single 5v supply and single-phase clock required pio architecture overview figure 1 illustrates ablock diagram of the z80 pio. the internal structure of the z80 pio consists of a z80 cpu bus interface, internal control logic, port a i/o logic, port b i/o logic, and interrupt control logic. the cpu bus interface logic allows the pio to interface directly to the z80 cpu with no other external logic. however, address decoders and/or line buffers may be required for large systems. the internal control logic synchronizes the cpu data bus to the peripheral device interfaces (port a and port b). the two i/o ports (a and b) are virtually identical and are used to interface directly to peripheral devices. figure 2 depicts the port i/o logic is composed of 6 registers with hand- shake control logic. the registers include: an 8-bit data input register, an 8-bit data output register, a 2-bit mode control register, an 8-bit mask register, an 8-bit input/output select register, and a 2-bit mask control register.

um008101-0601 parallel input/output the 2-bit mode control register is loaded by the cpu to select the desired operating mode (byte output, byte input, byte bidirectional bus, or bit control mode). all data transfer between the peripheral device and the cpu is achieved through the data input and data output registers. data may be written into the output register by the cpu or read back to the cpu from the input register at any time. the handshake lines associated with each port are used to control the data transfer between the pio and the peripheral device. figure 1. pio block diagram +5v gnd cpu interface 8 6 data bus pio control lines internal bus interrupt control lines internal control interrupt control data or control handshake 8 8 data or control handshake peripheral interface port a i/o port b i/o 3 logic

um008101-0601 parallel input/output figure 2. port i/o block diagram use the 8-bit mask register and the 8-bit input/output select register only in the bit control mode. in this mode, any of the eight peripheral data or control bus pins can be programmed to be an input or an output as speci- fied by the select register. the mask register is used in this mode in conjunction with a special interrupt feature. this feature allows an inter- rupt to be generated when any or all of the unmasked pins reach a speci- fied state (either high or low). the 2-bit mask control register specifies the active state desired (high or low) and if the interrupt should be generated when all unmasked pins are active (and condition) or when any unmasked pin is active (or condi- tion). this feature reduces the requirement for cpu status checking of the peripheral by allowing an interrupt to be automatically generated on specific peripheral status conditions. for example, in a system with three alarm conditions, an interrupt may be generated if any one occurs or if all three occur. handshake lines ready strobe interrupt requests mask control (2 bits) reg data output reg mode control reg (2 bits) output enable 8-bit peripheral data internal bus input data handshake control logic (2 bits) input/output select reg (8 bits) or control bus (8 bits) data input (8 bits) mask reg (8 bits)

um008101-0601 parallel input/output the interrupt control logic section handles all cpu interrupt protocol for nested priority interrupt structures. the priority of any device is determined by its physical location in a daisy-chain configuration. two lines are provided in each pio to form this daisy-chain. the device closest to the cpu has the highest priority. within a pio, port a interrupts have higher priority than those of port b. in the byte input, byte output or bidirectional modes, an interrupt can be generated whenever a new byte transfer is requested by the peripheral. in the bit control mode an interrupt can be generated when the peripheral status matches a programmed value. the pio provides for complete control of nested interrupts. that is, lower priority devices may not interrupt higher priority devices that have not had their interrupt service routine completed by the cpu. higher priority devices may interrupt the servicing of lower priority devices. when an interrupt is accepted by the cpu in mode 2, the interrupting device must provide an 8-bit interrupt vector for the cpu. this vector is used to form a pointer to a location in the computer memory where the address of the interrupt service routine is located. the 8-bit vector from the interrupting device forms the least-significant eight bits of the indirect pointer while the i register in the cpu provides the most-significant eight bits of the pointer. each port (a and b) has an independent interrupt vector. the least-significant bit of the vector is automatically set to a 0 within the pio because the pointer must point to two adjacent memory locations for a complete 16-bit address. the pio decodes the reti (return from interrupt) instruction directly from the cpu data bus so that each pio in the system knows at all times whether it is being serviced by the cpu interrupt service routine without any other communication with the cpu.

um008101-0601 parallel input/output pin description figure 3 illustrates a diagram of the z80 pio pin configuration. this section describes the function of each pin. d7-d0 z80 cpu data bus (bidirectional, tristate). this bus is used to transfer all data and commands between the z80 cpu and the z80 pio. d0 is the least-significant bit of the bus. b/a sel port b or a select (input, active high). this pin defines which port is accessed during a data transfer between the z80 cpu and the z80 pio. a low level on this pin selects port a while a high level selects port b. often, address bit a0 from the cpu is used for this selection function. c/d sel control or data select (input, active high). this pin defines the type of data transfer to be performed between the cpu and the pio. a high level on this pin during a cpu write to the pio causes the z80 data bus to be interpreted as a command for the port selected by the b/a select line. a lowlevelonthispinmeansthatthez80databusisbeingusedtotransfer data between the cpu and the pio. often, address bit al from the cpu is used for this function. ce chip enable (input, active low). a low level on this pin enables the pio to accept command or data inputs from the cpu during a write cycle or to transmit data to the cpu during a read cycle. this signal is generally a decode of four i/o port numbers that encompass ports a and b, data, and control.

um008101-0601 parallel input/output system clock (input). the z80 pio uses the standard z80 system clock to synchronize certain signals internally. this is a single phase clock. m1 machine cycle one signal from cpu (input, active low). this signal from the cpu is used as a sync pulse to control several internal pio opera- tions. when m1 is active and the rd signal is active, the z80 cpu is fetching an instruction from memory. conversely, when m1 is active and iorq is active, the cpu is acknowledging an interrupt. in addition, the m1 signal has two other functions within the z80 pio. 1. m1 synchronizes the pio interrupt logic. 2. when m1 occurs without an active rd or iorq signal, the pio logic enters a reset state. iorq input/output request from z80 cpu (input,activelow).theiorq signal is used in conjunction with the b/ a select, c/d select, ce ,and rd signals to transfer commands and data between the z80 cpu and the z80pio.whence ,rd ,andiorq are active, the port addressed by b/a transfers data to the cpu (a read operation). conversely, when ce and iorq areactivebutrd is not active, then the port addressed by b/a is written to from the cpu with either data or control information as speci- fied by the c/d select signal. also, if iorq and m1 are active simulta- neously, the cpu is acknowledging an interrupt and the interrupting port automatically places its interrupt vector on the cpu data bus if it is the highest priority device requesting an interrupt. rd read cycle status from the z80 cpu (input, active low). if rd is active, a memory read or i/o read operation is in progress. the rd signal is used with b/a select, c/d select, ce ,andiorq signals to transfer data from the z80 pio to the z80 cpu.

um008101-0601 parallel input/output iei interrupt enable in (input, active high). this signal is used to form a priority interrupt daisy-chain when more than one interrupt driven device is being used. a high level on this pin indicates that no other devices of higher priority are being serviced by a cpu interrupt service routine. ieo interrupt enable out (output, active high). the ieo signal is the other signal required to form a daisy-chain priority scheme. it is high only if iei is high and the cpu is not servicing an interrupt from this pio. thus, this signal blocks lower priority devices from interrupting while a higher priority device is being serviced by its cpu interrupt service routine. int interrupt request (output, open-drain, active low). when int is active, the z80 pio is requesting an interrupt from the z80 cpu. a7-a0 port a bus (bidirectional, tristate). this 8-bit bus is used to transfer data and/or status or control information between port a of the z80 pio and a peripheral device. a0 is the least-significant bit of the port a data bus. astb port a strobe pulse from peripheral device (input, active low). the meaning of this signal depends on the mode of operation selected for port a as follows: 1. output mode: the positive edge of this strobe is issued by the peripheral to acknowledge the receipt of data made available by the pio. 2. input mode: the strobe is issued by the peripheral to load data from the peripheral into the port a input register. data is loaded into the pio when this signal is active.

um008101-0601 parallel input/output 3. bidirectional mode: when this signal is active, data from the port a output register is gated onto port a bidirectional data bus. the positive edge of the strobe acknowledges the receipt of the data. 4. control mode: the strobe is inhibited internally. ardy register a ready (output, active high). the meaning of this signal depends on the mode of operation selected for port a as follows: 1. output mode: this signal goes active to indicate that the port a output register has been loaded and the peripheral data bus is stable and ready for transfer to the peripheral device. 2. input mode: this signal is active when the port a input register is empty and is ready to accept data from the peripheral device. 3. bidirectional mode: this signal is active when data is available in the port a output register for transfer to the peripheral device. in this mode, data is not placed on the port a data bus unless astb is active. 4. control mode: this signal is disabled and forced to a low state. b7-b0 port b bus (bidirectional, tristate). this 8-bit bus is used to transfer data and/or status or control information between port b of the pio and a peripheral device. the port b data bus is capable of supplying 1.5 ma @ 1.5v to drive darlington transistors. b0 is the least significant bit of the bus. bstb port b strobe pulse from peripheral device (input, active low). the meaning of this signal is similar to that of astb with the following exception: in the port a bidirectional mode, this signal strobes data from the peripheral device into the port a input register.

um008101-0601 parallel input/output brdy register b ready (output, active high). the meaning of this signal is similartothatofareadywiththefollowingexception:intheportabidi- rectional mode, this signal is high when the port a input register is empty and ready to accept data from the peripheral device. figure 3. pio pin functions z80?pio port a i/o a0 a1 a2 a3 a4 a5 a6 a7 ardy astb b0 b1 b2 b3 b4 b5 b7 brdy bstb b6 15 14 13 12 10 9 8 7 18 16 31 32 33 34 21 17 27 28 29 30 port b i/o cpu data d0 d1 a2 d3 d4 d5 d6 d7 port b/a sel control/data sel chip enable m1 iorq rd +5v int gnd 19 20 1 40 39 38 3 2 6 5 26 11 25 23 4 37 36 35 int enable in 24 int enable out 22 bus pio control interrupt control

um008101-0601 parallel input/output figure 4. 44-pin plcc pin assignments !

um008101-0601 parallel input/output figure 5. 44-pin qfp pin assignments 34 33 n/c cs1 clk/trg3 clk/trg2 n/c n/c clk/trg1 clk/trg0 n/c +5v n/c ieo iorq n/c zc/to2 zc/to1 n/c zc/to0 n/c rd gnd d7 cs0 reset ce n/c clk n/c m1 n/c iei n/c int d0 d1 d2 d3 n/c n/c n/c d4 d5 d6 n/c 44 22 12 11 1 cmos z80 pio

um008101-0601 parallel input/output figure 6. 40-pin dip pin assignments programming the pio reset the z80 pio automatically enters a reset state when power is applied. the reset state performs the following functions: 1. both port mask registers are reset to inhibit all port data bits. 2. port data bus lines are set to a high-impedance state and the ready handshake signals are inactive (low). mode 1 is automatically selected. 3. the vector address registers are not reset. 4. both port interrupt enable flip-flops are reset. 5. both port output registers are reset. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 z80 pio d 2 d 7 d 6 ce c/d b/a pa 7 pa 6 pa 5 pa 4 gnd pa 3 pa 2 pa 1 pa 0 astb bstb ardy d 0 d 1 d 3 d 4 d 5 m1 iorq rd pb 7 pb 6 pb 5 pb 4 pb 3 pb 2 pb 1 pb 0 +5v clk iei int ieo brdy

um008101-0601 parallel input/output in addition to the automatic power-on reset, the pio can be reset by applying an m1 signal without the presence of a rd or iorq signal. if no rd or iorq is detected during m1 , the pio enters the reset state immedi- ately after the m1 signal goes inactive. this reset allows a single external gate to generate a reset without a power-down sequence. the 40-pin pack- aging requires this routine. when the pio enters the internal reset state, it is held there until the pio receives a control word from the cpu. loading the interrupt vector the pio is designed to operate with the z80 cpu using the mode 2 inter- rupt response. this mode requires that an interrupt vector be supplied by the interrupting device. this vector is used by the cpu to form the address for the interrupt service routine of that port. this vector is placed on the z80 data bus during an interrupt acknowledge cycle by the highest priority device requesting service at that time. (refer to the z80 cpu user ? s manual section for details on how an interrupt is serviced by the cpu). the interrupt vector is loaded to the pio by writing a control word to the appropriate pio port using the following format: d0 functions as a flag bit, which when low, loads v7 through v1 to the vector register. at interrupt acknowledge, the vector of the interrupting port appears on the z80 data bus exactly as illustrated in the diagram above. signifies this control word is an interrupt vector v7 v6 v5 v4 d7 d6 d5 d4 d3 d0 d2 d1 v3 v2 v1 0

um008101-0601 parallel input/output selectinganoperatingmode pio port a allows operation in four modes: mode 0 (output mode), mode 1 (input mode), mode 2 (bidirectional mode), and mode 3 (control mode). the mode numbers are assigned for mnemonic significance: 0 = out, 1 = in, 2 = bidirectional. port b cannot operate in mode 2. the mode of operation must be established by writing a control word to the pio in the following format: listed in table 1, bits d7 and d6 form the binary code that designate mode of operation: bits d5 and d4 are ignored. bits d3-d0 must be set to 1111 to indicate set mode. selecting mode 0 enables any data written to the port output register by the cpu to be enabled onto the port data bus. the output register contents may be changed by writing a new data word to the port. also, the current contents of the output register may be read back to the z80 cpu by executing an input instruction. when mode 0 is active, a data write from the cpu causes the port ? s ready handshake line to go high, thereby notifying the peripheral that table 1. pio mode selection d7 d6 mode 0 0 0 (output) 0 1 1 (input) 1 0 2 (bidirectional) 113(control) mode word m1 m0 x x signifies mode word to be set d7 d6 d5 d4 d3 d0 d2 d1 11 11

um008101-0601 parallel input/output data is available. this signal remains high until a strobe is received from the peripheral. the rising edge of the strobe generates an interrupt (if it has been enabled) and causes the ready line to go inactive. this hand- shakeissimilartothoseusedbymanyperipheraldevices. by selecting mode 1, the port enters input mode. to initiate a handshake, the cpu performs an input read from the port. this activates the ready line, which signals the peripheral that data can be loaded to the empty input register. the peripheral device then strobes data to the port input register through the strobe line. again, the rising edge of the strobe causes an inter- rupt request (if it has been enabled) and deactivates the ready signal. data may be strobed to the input register regardless of the state of the ready signal if care is taken to prevent a data overrun condition. mode 2 is a bidirectional data transfer mode, utilizing all four handshake lines. therefore, only port a is used for mode 2 operation. mode 2 opera- tion uses the port a handshake signals for output control, and uses the port b handshake signals for input control. thus, both ardy and brdy may be active simultaneously. the only operational difference between mode 0 and the output portion of mode 2 is: data from the port a output register is allowed on the port data bus when astb is active. bidirectional capability is achieved only when astb is active. mode 3 operation is used for status and control applications and does not utilize the handshake signals. when mode 3 is selected, the next control word sent to the pio must define which port data bus lines are inputs and which are outputs. the format of the control word is depicted below: if any bit is set to a one, then the corresponding data bus line is used as an input. conversely, if the bit is reset, the line is used as an output. during mode 3 operation, the strobe signal is ignored and the ready line is held low. data may be written to a port or read from a port by the z80 cpu at any time during mode 3 operation. the data returned from a port to the i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 d7 d6 d5 d4 d3 d0 d2 d1

um008101-0601 parallel input/output cpu is composed of input data, which comes from port data bus lines assigned as inputs, and port output register data, which comes from lines assigned as outputs. setting the interrupt control word the interrupt control word for each port has the following format: if bit d7 = 1, the interrupt enable flip-flop of the port is set and the port may generate an interrupt. if bit d7 = 0, the enable flag is reset and inter- rupts may not be generated. if an interrupt is pending when the enable flag is set, the interrupt is then enabled to the cpu interrupt request line. bits d6, d5, and d4 are used only with mode 3 operation. however, setting bit d4 of the interrupt control word in any mode of operation causes a pending interrupt to be reset. these three bits allow interrupts in mode 3, but only when specific i/o lines go to defined states. bit d6 (and/or) defines the logical operation to be performed in port moni- toring. if bit d6 = 1, an and function is specified and if d6 = 0, an or function is specified. for example, if the and function is specified, all bits must go to a specified state before an interrupt is generated. conversely, the or function generates an interrupt if any specified bit goes to the active state. bit d5 defines the active polarity of the port data bus line to be monitored. if bit d5 = 1, the port data lines are monitored for a high state. when bit d5 = 0, the port data lines are monitored for a low state. if bit d4 = 1, the next control word sent to the pio must define a mask as follows: used in signifies interrupt d7 d6 d5 d4 d3 d0 enable int. and/ or high low masks follows d2 d1 mode 3 only 01 11 control word mb7 mb6 mb5 mb4 mb3 mb2 mb1 mb0 d7 d6 d5 d4 d3 d0 d2 d1

um008101-0601 parallel input/output only port lines whose mask bit is zero are monitored for generating an interrupt. when iorq is high, the forced state of ready prevents input register data from changing while the cpu is reading the pio. ready goes high again after the trailing edge of the iorq, as previously described timing output mode (mode 0) figure 7 illustrates the timing associated with mode 0 operation. an output cycle is always started by the execution of an output instruction by the cpu. a wr * pulse is generated by the pio during a cpu i/o write opera- tion and is used to latch the data from the cpu data bus to the addressed ports (a or b) output register. the rising edge of the wr * pulse then raises the ready flag after the next falling edge of , indicating that data is avail- able for the peripheral device. in most systems, the rising edge of the ready signal can be used as a latching signal in the peripheral device. the ready signal remains active until: (1) a positive edge is received from the strobe line, indicating that the peripheral has taken the data, or (2) if already active, ready is forced low for one and one-half cycles after the leading edge of iorq, but only if the port ? s output register is written to. ready returns high on the first falling edge of after the trailing edge of iorq . this guarantees that ready is low when port data is changing. the ready signal does not go inactive until a falling edge occurs on the clock ( ) line. the purpose of delaying the negative transition of the ready signal until after a negative clock transition is to allow a simple generation scheme for the strobe pulse. by connecting the ready line to the strobe line, a strobe with a duration of one clock period is generated with no other logic required. the positive edge of the strobe pulse automatically generates an int request when the interrupt enable flip-flop has been set and this device is the highest priority device requesting an interrupt.

um008101-0601 parallel input/output if the pio is not in a reset state, the output register may be loaded before mode 0 is selected. this allows the port output lines to become active in a user-defined state. figure 7. mode 0 (output) timing input mode (mode 1) figure 8 illustrates the timing of an input cycle. the peripheral initiates this cycleusingthestrobelineafterthecpuhasperformedadataread.alow level on this line loads data to the port input register and the rising edge of the strobe line activates the interrupt request line (int )iftheinterrupt enable is set and this is the highest priority requesting device. the next falling edge of the clock line ( ) resets the ready line to an inactive state, signifying that the input register is full and further loading must be inhibited until the cpu reads the data. the cpu, in the course of its interrupt service routine, reads the data from the interrupting port. when this occurs, the positive edge from the cpu rd signal raises the ready line with the next low going transition of , indicatingthatnewdatacanbeloadedtothe strobe ready wr * port output (8 bits) int wr *=rd ce c /d iorq

um008101-0601 parallel input/output pio. if already active, ready is forced low for one and one-half periods following the leading edge of iorq during a read of a pio port. figure 8. mode 1 (input) timing bidirectional mode (mode 2) this mode is a combination of mode 0 and mode 1, using all four hand- shake lines. because this mode requires all four lines, it is available only on port a. when this mode is used on port a, port b must be set to the bit control mode. the same interrupt vector is returned for a mode 3 interrupt on port b and an input transfer interrupt during mode 2 operation of port a. ambiguity is avoided if port b is operated in a polled mode and the port b mask register is set to inhibit all bits. figure 9 illustrates the timing for this mode. it is almost identical to that previously described for mode 0 and mode 1 with the port a handshake lines used for output control and the port b lines used for input control. the difference between the two modes is that, in mode 2, data is allowed out onto the bus only when the a strobe is low. the rising edge of this strobe can be used to latch the data to the peripheral because the data remains stable ready port input (8 bits) strobe int rd * sample rd *=rd ce c /d iorq

um008101-0601 parallel input/output after this edge has risen. the input portion of mode 2 operates identically to mode 1. notice that both port a and port b must have their interrupts enabled to achieve an interrupt-driven, bidirectional transfer. the peripheral must not gate data onto a port data bus while astb is active. bus contention is avoided when the peripheral uses bstb to gate input data onto the bus. the pio uses the bstb low level to latch this data. the data can be disabled from the bus immediately after the strobe rising edge. this is because the pio has been designed with a zero hold time requirement for the data when latching in this mode. this gating structure can be used by the peripheral. figure 9. port a, mode 2 (bidirectional) timing control mode (mode 3) the control mode does not utilize the handshake signals, therefore a normal port write or port read can be executed at any time. when writing, the data is latched to output registers with the same timing as mode 0. ardy is forced low whenever port a is operated in mode 3. brdy is held low whenever port b is operated in mode 3 unless port a is in mode 2. in the latter case, the state of brdy is not affected. wr * sample wr * =rd ce c /d iorq data out data in ardy astb port a data bus int bstb brdy

um008101-0601 parallel input/output when reading the pio, the data returned to the cpu is composed of output register data from port data lines assigned as outputs and input register data from port data lines assigned as inputs. the input register contains data that was present immediately prior to the falling edge of rd . see figure 10. an interrupt is generated if interrupts from the port are enabled and the data on the port data lines satisfies the logical equation defined is not generated until a change occurs in the status of the logical equation. a mode 3 interrupt is generated only when the result of a mode 3 logical operation changes from false to true. for example, mode 3 logical equa- tion is an or function. an unmasked port data line becomes active and an interrupt is requested. if a second unmasked port data line becomes active concurrently with the first, a new interrupt is not requested because a change in the result of the mode 3 logical operation has not occurred. if the result of a logical operation becomes true immediately prior to or during m1 an interrupt is requested after the trailing edge of m1 figure 10. control mode (mode 3) timing data in data word 1 data word 2 data match occurs here t 1 t 2 t w *t 3 *timing diagram refers to bit mode read d7 ? d0 rd iorq int port data bus dataword1placedonbus

um008101-0601 parallel input/output interrupt servicing after an interrupt is requested by the pio, the cpu sends out an interrupt acknowledge (m1 and iorq ). during this time, the interrupt logic of the pio determines which port has the highest priority interrupt. (this is a device which has an interrupt enable input high and an interrupt enable output low). to insure that the daisy-chain enable lines stabilize, devices are inhibited from changing their interrupt request status when m1 is active. the highest priority device places the contents of its interrupt vector register onto the z80 data bus during interrupt acknowledge. figure 11 illustrates the timing associated with interrupt requests. during m1 time, no new interrupt requests can be generated. this allows time for the lnt enable signals to ripple through up to four pio circuits. the pio, with iei high and ieo low during inta , places the 8-bit interrupt vector of the appropriate port on the data bus at this time. if an interrupt requested by the pio is acknowledged, the requesting port is under service . the ieo of this port remains low until a return from interrupt instruction (reti) is executed, during which time the iei of the port is high. if an interrupt request is not acknowledged, ieo is forced high for one m1 cycle after the pio decodes the op code ed. this action guarantees that the 2-byte reti instruction is decoded by the correct pio port (figure 12). figure 13 illustrates a typical nested interrupt sequence that could occur with four ports connected in the daisy-chain. in this sequence, port 2a requests and is granted an interrupt. while this port is being serviced, a higher priority port (1b) requests and is granted an interrupt. the service routine for the higher priority port is completed and a reti instruction is executed, indicating to the port that its routine is complete. the service routine of the lower priority port is then complete.

um008101-0601 parallel input/output figure 11. interrupt acknowledge timing figure 12. return from interrupt cycle m1 iorq int iorq and m1 indicate interrupt ieo iei last t state t 1 t 2 t w * t 3 t w * sample int acknowledge (inta ) ieo clk iei rd m1 t 1 t 2 t 3 t 4 d 7 ? d 0 t 1 t 2 t 3 t 4 t 1 ed 4d

um008101-0601 parallel input/output figure 13. daisy-chain interrupt servicing applications extending the interrupt daisy-chain without external logic, a maximum of four z80 pio devices may be daisy- chained into a priority interrupt structure. this limitation allows the inter- rupt enable status (ieo) to ripple through the entire daisy-chain between the beginning of m1 and the beginning of iorq during an interrupt acknowledge cycle. the interrupt enable status cannot change during m1 , therefore, the vector address returned to the cpu is assured to be from the highest priority device that requested an interrupt. iei ieo hi + iei ieo hi + iei ieo hi + iei ieo hi + iei ieo hi iei ieo hi iei ieo hi iei ieo hi iei ieo hi iei ieo hi + iei ieo hi iei ieo hi iei ieo lo iei ieo hi iei ieo hi iei ieo hi iei ieo lo iei ieo lo iei ieo lo iei ieo hi hi lo lo lo hi port 2b port 1b port 2a under service service suspended service resumed service complete 5. second ? reti ? instruction issued on completion of port 2a service routine. 4. port 1b service routine complete, ? reti ? issued, port 2a service resumed. 3. port 1b1 interrupts, suspends servicing of port 2a. 2. port 2a requests an interrupt and is acknowledged. 1. priority interrupt daisy chain before any interrupt occurs. service complete under service port 1a hi g h est p r i or i ty ch anne l

um008101-0601 parallel input/output if more than four pio devices must be accommodated, a look-ahead struc- ture may be used as shown in figure 14. with this technique, more than thirty pios may be chained together using standard ttl logic. figure 14. a method of extending the interrupt priority daisy-chain i/o device interface in this example, the z80 pio is connected to an i/o terminal device, which communicates over an 8-bit parallel bidirectional data bus as illustrated in figure 15. mode 2 operation (bidirectional) is selected by sending the following control word to port a: next, the appropriate interrupt vector is loaded (refer to z80 cpu user ? s manual for details on the operation of the interrupt). z80 cpu ieo iei ieo iei ieo iei ieo iei data bus +v pi0 pi0 pi0 pi0 ieo iei ieo iei ieo iei ieo iei pi0 pi0 pi0 pi0 mode control xx d7 d6 d5 d4 d3 d0 d2 d1 11 11 10

um008101-0601 parallel input/output interrupts are then enabled by the rising edge of the first m1 after the inter- rupt mode word is set unless that first m1 defines an interrupt acknowledge cycle. if a mask follows the interrupt mode word, interrupts are enabled by the rising edge of the first m1 following the setting of the mask. data can now be transferred between the peripheral and the cpu. the timing for this transfer is as described in ? timing ? on page 192. figure 15. example of i/o interface v5 v4 d7 d6 d5 d4 d3 d0 d2 d1 v3 v2 v1 v0 v1 v6 "# $$%&''#(' $$%&'' (' &)*$&% "# &%+,-./ *%0# .0.#('

um008101-0601 parallel input/output control interface a typical control mode application is illustrated in figure 16. in this example, an industrial process is to be monitored. the occurrence of any abnormal operating condition is to be reported to a z80 cpu-based control system. the process control and status word has the following format: the pio may be used as follows. first, port a is set for mode 3 operation by writing the following control word to port a. whenever mode 3 is selected, the next control word sent to the port must be an i/o select word. in this example, port data lines a5, a3, and a0 are selected as inputs, and the following control word is written: next, the appropriate interrupt vector must be loaded (refer to the z80 cpu user ? s manual for details): an interrupt control word is next sent to the port: the mask word following the interrupt mode word is: d7 d6 d5 d4 d3 d0 halt processing d2 d1 special tes t turn on power power failure alarm te m p . alarm turn on heaters pressurize system pressure alarm 11xx d7 d6 d5 d4 d3 d0 d2 d1 11 11 001 0 d7 d6 d5 d4 d3 d0 d2 d1 10 01 v5 v4 d7 d6 d5 d4 d3 d0 d2 d1 v3 v2 v1 0 v1 v6 interrupt control 11 d7 d6 d5 d4 d3 d0 d2 d1 01 11 10 enable interrupts or logic active high mask follows

um008101-0601 parallel input/output if a sensor puts a high level on lines a5, a3, or a0, an interrupt request is generated. the mask word may select any combination of inputs or outputs to cause an interrupt. for example, if the mask word above is: then an interrupt request would also occur if bit a7 (special test) of the output register was set. assume that the following port assignments are to be used: e0h = port a data e1h = port b data e2h = port a control e3h = port b control all port numbers are in hexadecimal notation. this particular assignment of port numbers is convenient because a0 of the address bus can be used as the port b/a select and a1 of the address bus can be used as the control/ data select. the chip enable is the decode of cpu address bits a7 through a2 ( 111000 ). note: when only a few peripheral devices are being used, a chip enable decode may not be required because a higher order address bit may be used directly. selects a5, a3, and a0 to be monitored 01 d7 d6 d5 d4 d3 d0 d2 d1 01 10 11 01 d7 d6 d5 d4 d3 d0 d2 d1 01 10 01

um008101-0601 parallel input/output figure 16. control mode application z80 cpu z80 pio industrial processing system b/a c/d ce a15 ? a0 d7 ? d0 spec. test turn on pwr. pwr. fail alm. halt temp. a lm . htrs. on press. sys press. alm. a7 a5 a4 a3 a2 a1 a0 a6 port a bus address decoder

um008101-0601 parallel input/output programming summary overview this section discusses the load interrupt vector, set mode, set interrupt control registers. load interrupt vector set mode when selecting mode 3, the next word must set the i/o register: m1 m0 mode 00output 0 1 input 1 0 bidirectional 1 1 bit control v5 v4 d7 d6 d5 d4 d3 d0 d2 d1 v3 v2 v1 0 v1 v6 m1 m0 x x d7 d6 d5 d4 d3 d0 d2 d1 11 11

um008101-0601 parallel input/output set interrupt control if the mask follows bit is high, the next control word written to the port must be the mask: in addition, the interrupt enable flip-flop of a port may be set or reset without modifying the remainder of the interrupt control word. this is accomplished by issuing the following command: used in enable int. and/ or high low masks follows mode3only 01 11 mb7 mb6 mb5 mb4 mb3 mb2 mb1 mb0 xx 00 11 x enable int.
z80 cpu peripherals user manual um008101-0601 serial input/output 207 serial input/output overview the z80 serial input/output (sio) is a dual-channel multi-function peripheral component designed to satisfy a wide variety of serial data communications requirements in microcomputer systems. the z80 sio functions as a serial-to-parallel, parallel-to-serial converter/controller, and is systems-software configurable to allow optimization for a given serial data communications application. the z80 sio is capable of handling asynchronous and synchronous byte- oriented protocols such as ibm bisync and synchronous bit-oriented protocols such as hdlc and ibm sdlc. this versatile device also supports virtually any other serial protocol for applications other than data communications, such as cassette or floppy disk interfaces. the z80 sio can generate and check crc codes in any synchronous mode and can be programmed to check data integrity in various modes. the device also has features for modem controls in both channels. in applica- tions where these controls are not needed, the modem controls can be used for general-purpose i/o. features cmos and nmos version 40-pin dip, 44-pin plcc/qfp packages single 5v power supply single-phase 5v clock

um008101-0601 serial input/output 208 ttl-compatible inputs and outputs two independent full-duplex channels data rates in synchronous or isosynchronous modes: ? 0-800k bits/second with 4 mhz system clock rate ? 0-1.2m bits/second with 6 mhz system clock rate ? 0-2.5m bits/second with 10 mhz system clock rate receiver data registers quadruply buffered; transmitter doubly buffered asynchronous features: ? 5, 6, 7, or 8 bits per character ? 1, 1 1/2, or 2 stop bits ? even, odd, or no parity ? x1, x16, x32, and x64 clock modes ? break generation and detection ? parity, overrun, and framing error detection binary synchronous features: ? internal or external character synchronization ? one or two sync characters in separate registers ? automatic sync character insertion ? crc generation and checking hdlc and ibm sdlc features: ? abort sequence generation and detection ? automatic zero insertion and deletion ? automatic flag insertion between messages ? address field recognition ? 1-field residue handling ? valid receive messages protected from overrun
z80 cpu peripherals user manual um008101-0601 serial input/output 209 crc generation and checking separate modem control inputs and outputs for both channels crc-16 or crc-ccitt block check daisy-chain priority interrupt logic provides automatic interrupt vectoring without external logic modem status can be monitored figure 100. z80 sio block diagram cpu bus i/o +5v gnd data control international control logic channel a read/write registers channel b read/write registers international control logic 8 6 interrupt control lines channel b discrete control and status (channel a) channel a modem or other serial data channel clocks discrete control and status (channel b) sync wait/ready controls modem or other controls serial data channel clocks sync wait/ready

um008101-0601 serial input/output 210 pin description pin functions d7-d0 system data bus (bidirectional, tristate). the system data bus transfers data and commands between the cpu and the z80 sio. d0 is the least-significant bit. b/ a channel a or b select (input, high selects channel b). this input defines which channel is accessed during a data transfer between the cpu and the z80 sio. address bit a0 from the cpu is often used for the selec- tion function. c/d control or data select (input, high selects control). this input defines the type of information transfer performed between the cpu and the z80 sio. a high at this input during a cpu write to the z80 sio causes the information on the data bus to be interpreted as a command for the channel selected by b/a .alowatc/d indicates that the information on the data bus is data. address bit a1 is often used for this function. ce chip enable (input, active low). a low level at this input enables the z80 sio to accept command or data inputs from the cpu during a write cycle, or to transmit data to the cpu during a read cycle. system clock (input). the z80 sio uses the standard Z80A system clock to synchronize internal signals. this is a single-phase clock. m1 machine cycle one (input from z80 cpu, active low). when m1 is active and rd is also active, the z80 cpu is fetching an instruction from memory; when m1 is active while iorq is active, the z80 sio accepts m1 and iorq as an interrupt acknowledge if the z80 sio is the highest priority device that has interrupted the z80 cpu. iorq input/output request (input from cpu, active low). iorq is used in conjunction with b/a ,c/d ,ce ,andrd to transfer commands and data between the cpu and the z80 sio. when ce ,rd ,andiorq are all active, the channel selected by b/a transfers data to the cpu (a read operation).
z80 cpu peripherals user manual um008101-0601 serial input/output 211 when ce and iorq are active, but rd is inactive, the channel selected by b/a is written to by the cpu with either data or control information as specified by c/d . as mentioned previously, if iorq and m1 are active simultaneously, the cpu is acknowledging an interrupt and the z80 sio automatically places its interrupt vector on the cpu data bus if it is the highest priority device requesting an interrupt. rd read cycle status (input from cpu, active low). if rd is active, a memory or i/o read operation is in progress. rd is used with b/a ,ce , and iorq to transfer data from the z80 sio to the cpu. reset reset (input, active low). a low /reset disables both /reset and transmitters, forces txda and txdb marking, forces the modem controls high and disables all interrupts. the control registers must be rewritten after the z80 sio is reset and before data is transmitted or received. iei interrupt enable in (input, active high). this signal is used with ieo to form a priority daisy-chain when there is more than one interrupt- driven device. a high on this line indicates that no other device of higher priority is being serviced by a cpu interrupt service routine. ieo interrupt enable out (output, active high). ieo is high only if iei is high and the cpu is not servicing an interrupt from this z80 sio. there- fore, this signal blocks lower priority devices from interrupting while a higher priority device is being serviced by its cpu interrupt service routine. int interrupt request (output, open-drain, active low). when the z80 sio is requesting an interrupt, it pulls int low. w/rdya ,w/rdyb wait/ready a , wait/ready b (outputs, open-drain when programmed for wait function, driven high and low when programmed for ready function). these dual-purpose outputs may be programmed as ready lines for a dma controller or as wait lines that synchronize the cpu to the z80 sio data rate. the reset state is open-drain. csta ,cstb clear to send (inputs, active low). when programmed as auto enables, a low on these inputs enables the respective transmitter. if not programmed as auto enables, these inputs may be programmed as

um008101-0601 serial input/output 212 general-purpose inputs. both inputs are schmitt-trigger buffered to accommodate slow-risetime inputs. the z80 sio detects pulses on these inputs and interrupts the cpu on both logic level transitions. the schmitt-trigger inputs do not guarantee a specified noise-level margin. dcda , dcdb data carrier detect (inputs, active low). these signals are similar to the cts inputs, except they can be used as receiver enables. rxda, rxdb receive data (inputs, active high). txda, txdb transmit data (outputs, active high). rxca, rxcb* receiver clocks (inputs). see the following section on bonding options. the receive clocks may be 1, 16, 32, or 64 times the data rate in asynchronous modes. receive data is sampled on the rising edge of rxc . txca ,txcb * transmitter clocks (inputs). see section on bonding options. in asynchronous modes, the transmitter clocks may be 1, 16, 32, or 64 times the data rate. the multiplier for the transmitter and the receiver must be the same. both the txc and rxc inputs are schmitt-trigger buff- ered for relaxed rise- and fall-time requirements (no noise margin is speci- fied). txd changes on the falling edge of txc . these clocks may be directly driven by the z80 ctc (counter timer circuit) for fully programmable baud rate generation. rtsa ,rtsb request to send (outputs, active low). when the /rts bit is set, the rts output goes low. when the rts bit is reset in the asynchro- nous mode, the output goes high after the transmitter is empty. in synchro- nous modes, the rts pin strictly follows the state of the rts bit. both pins can be used as general-purpose outputs. dtra ,dtrb data terminal, ready (outputs, active low). see note on bonding options. these outputs follow the state programmed into the dtr bit. they can also be programmed as general-purpose outputs. synca , syncb synchronization (inputs/outputs, active low). these pins can act either as inputs or outputs. in the asynchronous receive mode,
z80 cpu peripherals user manual um008101-0601 serial input/output 213 they are inputs similar to cts and dcd . in this mode, the transitions on these lines affect the state of the sync/hunt status bits in rr0. in the external sync mode, these lines also act as inputs. when external synchro- nization is achieved, sync must be driven low on the second rising edge of rxc after that rising edge of rxc on which the last bit of the sync char- acter was received. in other logic must wait for two full receive clock cycles to activate the sync input. when sync is forced low, keep it low until the cpu notifies the external sync logic that synchronization has been lost or that a new message is about to start. character assembly begins on the rising edge of rxc that immediately precedes the falling edge of sync in the external sync mode. in the internal synchronization mode (monosync and bisync), these pins function as outputs that are active during the part of the receive clock (rxc ) cycle in which sync characters are recognized. the sync condition is not latched, therefore, these outputs are active each time a sync pattern is recog- nized, regardless of character boundaries. bonding options theconstraintsofa40-pinpackagemakeitimpossibletobringoutthe receive clock, transmit clock, data terminal ready, and sync signals for both channels. therefore, channel b must sacrifice a signal or have two signals bonded together. because user requirements vary, three bonding options are offered: z80 sio/0 contains all four signals, but txcb and rxcd are bonded together ( figure 101 ). z80 sio/1 sacrifices dtrb and keeps txcb ,rxcd and syncb ( figure 103 ). z80 sio/2 sacrifices syncb and keeps txcb ,rxcb and dtrb ( figure 105 ). the 44-pin package version sio/3 (qfp) and sio/4 (plcc) have all signals ( figure 107 and figure 108 ).

um008101-0601 serial input/output 214 figure 101. z80 sio/0 functions z80 sio/0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 d0 d2 d6 d4 iorq ce b/a c/d rd gnd w /rdyb syncb rxdb rxtxcb txdb dtrb rtsb ctsb dcdb reset 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 d1 d3 d7 d5 int iei ieo m1 vdd w /rdya synca rxda rxca txca txda dtra rtsa ctsa dcda
z80 cpu peripherals user manual um008101-0601 serial input/output 215 figure 102. z80 sio/0 pin assignments z80 ? sio/0 ch-a rxda rxca txda txca synca w /rdya rtsa ctsa dtra dcda rxdb rxtxcb txdb syncb w /rdyb ctsb dtrb dcdb rtsb 12 13 15 14 11 10 17 18 16 19 30 24 23 25 22 28 27 26 29 ch-b cpu data bus sio control d0 d1 d2 d3 d4 d5 d6 d7 ce reset m1 iorq rd 5v gnd int iei ieo 40 1 39 2 38 3 37 4 35 21 31 20 5 6 7 8 36 32 9 from cpu daisy chain interrupt control modem control modem control 33 34 c/d b/a

um008101-0601 serial input/output 216 figure 103. z80 sio/1 pin functions z80 sio/1 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 d0 d2 d6 d4 iorq ce b/a c/d rd gnd w /rdyb syncb rxdb rxcb txcb txdb rtsb ctsb dcdb reset 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 d1 d3 d7 d5 int iei ieo m1 vdd w /rdya synca rxda rxca txca txda dtra rtsa ctsa dcda
z80 cpu peripherals user manual um008101-0601 serial input/output 217 figure 104. z80 sio/1 pin assignments z80 ? sio/1 ch-a rxda rxca txda txca synca w /rdya rtsa ctsa dtra dcda rxdb rxtxcb txcb syncb w /rdyb ctsb dcdb rtsb 12 13 15 14 11 10 17 18 16 19 30 24 23 22 28 27 26 29 ch-b cpu data bus sio control d0 d1 d2 d3 d4 d5 d6 d7 ce reset m1 iorq rd 5v gnd int iei ieo f 40 1 39 2 38 3 37 4 35 21 31 20 5 6 7 8 36 32 9 from cpu daisy chain interrupt control modem control txdb 25 modem control 33 34 c/d b/a

um008101-0601 serial input/output 218 figure 105. z80 sio/2 pin functions z80 sio/2 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 d0 d2 d6 d4 iorq b/a c/d rd gnd w /rdyb rxdb rxcb txcb txdb dtrb rtsb ctsb dcdb reset 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 d1 d3 d7 d5 int iei ieo m1 vdd w /rdya synca rxda rxca txca txda dtra rtsa ctsa dcda f ce
z80 cpu peripherals user manual um008101-0601 serial input/output 219 figure 106. z80 sio/2 pin assignments z80 ? sio/2 ch-a rxda rxca txda txca synca w /rdya rtsa ctsa dtra dcda rxdb rxcb txcb w /rdyb ctsb dcdb rtsb 12 13 15 14 11 10 17 18 16 19 30 24 23 22 29 28 27 ch-b cpu data bus sio control d0 d1 d2 d3 d4 d5 d6 d7 ce reset m1 iorq rd 5v gnd int iei ieo f 40 1 39 2 38 3 37 4 35 21 31 20 5 6 7 8 36 32 9 from cpu daisy chain interrupt control modem control txdb 26 modem control 33 34 c/d b/a dtrb 25

um008101-0601 serial input/output 220 figure 107. z80 sio/3 pin assignments 34 33 iei ieo m1 +5v w /rdya n/c synca rxda rxca txca txda ce b/a c/d rd gnd n/c w /rdyb syncb rxdb rxcb txcb int d7 d5 d3 d1 n/c d0 d2 d4 d6 iorq dtra rtsa ctsa dcda clk reset dcdb ctsb rtsb dtrb txdb 44 22 12 11 1 cmos z80 z804c43 sio/3
z80 cpu peripherals user manual um008101-0601 serial input/output 221 figure 108. z80 sio/4 pin assignments iei ieo m1 +5v w /rdya synca rxda rxca txca txda b/a c/d rd gnd w /rdyb syncb rxdb rxcb txcb txdb dtra rtsa ctsa dcda clk reset dcdb ctsb rtsb dtrb n/c z80 sio/4 nc 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 int d7 d5 d3 d1 d0 d2 d4 d6 iorq ce n/c 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28

um008101-0601 serial input/output 222 architecture overview the device internal structure includes a z80 cpu interface, internal control and interrupt logic, and two full-duplex channels. associated with each channel are read and write registers, and discrete control and status logic that provides the interface to modems or other external devices. the read and write register group includes five 8-bit control registers, two sync-character registers, and two status registers. the interrupt vector is written into an additional 8-bit register (write register 2) in channel b that may be read through read register 2 in channel b. the registers for both channels are designated as follows: wr7 ? wr0 ? write registers 0 through 7 rr2 ? rr0 ? read registers 0 through 2 the bit assignment and functional grouping of each register is configured to simplify and organize the programming process. table 1 and table 2 illus- trate the functions assigned to each read or write register. the logic for both channels provides formats, synchronization, and valida- tion for data transferred to and from the channel interface. the modem control inputs clear to send (cts ) and data carrier detect (dcd )are monitored by the discrete control logic under program control. all the modem control signals are general purpose and can be used for functions other than modem control. for automatic interrupt vectoring, the interrupt control logic determines which channel and which device within the channel has the highest priority. priority is fixed with channel a assigned a higher priority than channel b; receive, transmit and external/status interrupts are prioritized in that order within each channel.
z80 cpu peripherals user manual um008101-0601 serial input/output 223 data path the transmit and receive data path for each channel is depicted in figure 109 . the receiver contains three 8-bit buffer registers in a fifo arrangement (to provide a 3-byte delay) in addition to the 8-bit receive shift register. this arrangement creates additional time for the cpu to service an interrupt at the beginning of a block of high-speed data. the receive error fifo stores parity and framing errors and other types of status information for each of the three bytes in the receive data fifo. incoming data is routed through one of several paths depending on the mode and character length. in the asynchronous mode, serial data is table 1. write register functions bit function wr0 register pointers, crc initialize, initialization commands for the various modes and more wr1 transmit/receive interrupt and data transfer mode definition wr2 interrupt vector (channel b only) wr3 receive parameters and controls wr4 transmit/receive miscellaneous parameters and modes wr5 transmit parameters and controls wr6 sync character or sdlc address field wr7 sync character or sdlc flag table 2. read register functions bit function rr0 transmit/receive buffer status, interrupt status, and external status rr1 special receive condition status rr2 modified interrupt vector (channel b only)

um008101-0601 serial input/output 224 entered in the 3-bit buffer if the data has a character length of seven or eight bits, or is entered in the 8-bit receive shift register if the data has a length of five or six bits. in the synchronous mode, the data path is determined by the phase of the receive process currently in operation. a synchronous receive operation begins with the receiver in the hunt phase, during which the receiver searches the incoming data stream for a bit pattern that matches the prepro- grammed sync characters for flags in the sdlc mode. if the device is programmed for monosync hunt, a match is made with a single sync char- acter stored in wr7. in bisync hunt, a match is made with dual sync char- acters stored in wr6 and wr7. in either case, the incoming data passes through the receive sync register, and is compared against the programmed sync character in wr6 or wr7. in the monosync mode, a match between the sync character programmed to wr7 and the character assembled in the receive sync register establishes synchronization. in the bisync mode, however, incoming data is shifted to the receive shift register while the next eight bits of the message are assembled in the receive sync register. the match between the assembled character in the receive sync registers with the programmed sync character in wr6 and wr7 establishes synchronization. when synchronization is established, incoming data bypasses the receive sync register and directly enters the 3-bit buffer. in the sdlc mode, incoming data first passes through the receive sync register, which continuously monitors the receive data stream and performs zero deletion when indicated. upon receiving five contiguous 1s, the sixth bit is inspected. if the sixth bit is a 0, it is deleted from the data stream. if the sixth bit is a 1, the seventh bit is inspected. if the seventh bit is a 0, a flag sequence has been received; if it is a 1, an abort sequence has been received. the reformatted data enters the 3-bit buffer and is transferred to the receive shift register. the sdlc receive operation also begins in the hunt phase,
z80 cpu peripherals user manual um008101-0601 serial input/output 225 during which the z80 sio tries to match the assembled character in the receive shift register with the nag pattern in wr7. when the first flag char- acter is recognized, all subsequent data is routed through the same path, regardless of character length. although the same crc checker is used for both sdlc and synchronous data, the data path taken for each mode is different. in bisync protocol, a byte-oriented operation requires that the cpu decide to include the data character in crc. to allow the cpu ample time to make this decision, the z80 sio provides an 8-bit delay for synchronous data. in the sdlc mode, no delay is provided because the z80 sio contains logic that determines the bytes on which crc is calculated. the transmitter has an 8-bit transmit data register that is loaded from the internal data bus and a 20-bit transmit shift register that can be loaded from wr6, wr7, and the transmit data register. wr6 and wr7 contain sync characters in the monosync or bisync modes, or address field (one char- acter long) and flag respectively in the sdlc mode. during synchronous modes, information contained in wr6 and wr7 is loaded to the transmit shift register at the beginning of the message and, as a time filler, in the middle of the message if a transmit underrun condition occurs. in the sdlc mode, the flags are loaded to the transmit shift register at the begin- ning and end of message. asynchronous data in the transmit shift register is formatted with start and stop bits and is shifted out to the transmit multiplexer at the selected clock rate. synchronous (monosync or bisync) data is shifted out to the transmit multiplexer and also to the crc generator at the x1 clock rate. sdlc/hdlc data is shifted out through the zero insertion logic, which is disabled while the flags are sent. for all other fields (address, control, and frame check) a 0 is inserted following five contiguous 1s in the data stream. the crc generator result for sdlc data is also routed through the zero insertion logic.

um008101-0601 serial input/output 226 figure 109. transmit and receive data path functional description the functional capabilities of the z80 sio are described in two ways: as a data communications device, and as a z80 family peripheral. as a data communications device, the s80 sio transmits and receives serial data, and meets the requirements of various data communications protocols. as a z80 family peripheral, it interacts with the z80 cpu and other z80 peripheral, circuits, and shares their data, address and control receive error logic i/o data buffer cpu i/o internal data bus receive clock logic async data crc delay register (8 bits) sync- crc rxda rxca hunt mode (bisync) 3bits 1-bit delay crc checker sync sdlc-crc crc result sync-crc transmit clock logic sync data sdlc-crc async data transmit multiplexer and txda txca 20-bit transmit shift register start bit transmit wr7 sync and zero delay register wr6 sync register data sdlc data crc generator 2-bit zero (5 bits) insert register delete receive s.r. (8 bits) receive error fifo receive error fifo
z80 cpu peripherals user manual um008101-0601 serial input/output 227 busses, as well as being a part of the z80 interrupt structure. as a peripheral to other microprocessors, the z80 sio offers valuable features such as non- vectored interrupts, polling and simple handshake capabilities. the first part of the following functional description describes the interac- tion between the cpu and z80 sio. the second part introduces its data communications capabilities. i/o capabilities the z80 sio offers the choice of polling, interrupt (vectored or non- vectored), and block transfer modes to transfer data, status, and control information to and from the cpu. the block transfer mode can be imple- mented under cpu or dma control. polling the polled mode avoids interrupts. status registers rr0 and rr1 are updated at appropriate times for each function being performed, for example, crc error status valid at the end of the message. all the z80 sio interrupt modes must be disabled to operate the device in a polled environment. while in polling sequence, the cpu examines the status contained in rr0 for each channel. the rr0 status bits serve as an acknowledge to the poll inquiry. the two rr0 status bits d0 and d2 indicate that a receive or transmit data transfer is needed. the status also indicates error or other special status conditions (see ? programming ? on page 272 ). the special receive condition status contained in rr1 does not have to be read in a polling sequence because the status bits in rr1 are accompanied by a receive character available status in rr0 interrupts the z80 sio offers an elaborate interrupt scheme to provide fast interrupt response in real-time applications. as covered earlier, channel b registers wr2 and rr2 contain the interrupt vector that points to an interrupt service

um008101-0601 serial input/output 228 routine in the memory. to service operations in both channels and to elimi- nate the necessity of writing a status analysis routine, the z80 sio can modify the interrupt vector in rr2 so that it points directly to one of eight interrupt service routines. this is done under program control by setting a program bit (wr1, d2) in channel b called ? status affects vector. ? when this bit is set, the interrupt vector in wr2 is modified according to the assigned priority of the various interrupting conditions. the table in ? write register 1 ? on page 279 lists the modification details. transmit interrupts, receive interrupts, and external/ status interrupts are the main sources of interrupts ( figure 110 ). each interrupt source is enabled under program control with channel a having a higher priority than channel b, and with receiver, transmit, and external/status inter- rupts prioritized in that order within each channel. when the transmit interrupt is enabled, the cpu is interrupted by the transmit buffer becoming empty. this implies that the transmitter had a data character written into it so it can become empty. when enabled, the receiver can interrupt the cpu in one of three ways: interrupt on first receive character interrupt on all receive characters interrupt on a special receive condition interrupt on first character is typically used with the block transfer mode. interrupt on all receive characters has the option of modifying the inter- rupt vector in the event of a parity error. the special receive condition interrupt can occur on a character or message basis, for example, end-of- frame interrupt in sdlc. the special receive condition can cause an interrupt only if the interrupt on first receive character or interrupt on all receive characters mode is selected. in interrupt on first receive character, an interrupt can occur from special receive conditions (except parity error) after the first receive character interrupt, for example, receive overrun interrupt. the main function of the external/status interrupt is to monitor the signal transitions of the cts ,dcd ,andsync pins; however, an external/status
z80 cpu peripherals user manual um008101-0601 serial input/output 229 interrupt is also caused by a transmit underrun condition or by the detec- tion of a break (asynchronous mode) or abort (sdlc mode) sequence in the data stream. the interrupt caused by the break/abort sequence has a special feature that allows the z80 sio to interrupt when the break/abort sequence is detected or terminated. this feature facilitates the proper termi- nation of the current message, correct initialization of the next message, and the accurate timing of the break/abort condition in external logic. cpu/dma block transfer the z80 sio provides a block transfer mode to accommodate cpu block transfer functions and dma controllers (z80-dma or other designs). the block transfer mode uses the wait /ready output in conjunction with the wait/ready bits of write register 1. the wait /ready output can be defined under software control as a wait line in the cpu block transfer mode or as a ready line in the dma block transfer mode. to a dma controller, the z80 sio ready output indicates that the z80 sio is ready to transfer data to or from memory. to the cpu, the wait output indicates that the z80 sio is not ready to transfer data, thereby requesting the cpu to extend the i/o cycle. the programming of bits 5, 6, and 7 of write register 1 and the logic states of the wait /ready line are defined in ? write register 1 ? on page 279 . data communications capabilities in addition to the i/o capabilities previously discussed, the z80 sio provides two independent full-duplex channels as well as asynchronous, synchronous, and sdlc (hdlg) operational modes. these modes facili- tate the implementation of commonly used data communications protocols. the specific features of these modes are described in the following sections. to preserve the independence and completeness of each section, someinformationcommontoallmodesisrepeated.

um008101-0601 serial input/output 230 figure 110. interrupt structure asynchronous operation overview to receive or transmit data in the asynchronous mode, the z80 sio must be initialized with the following parameters: character length, clock rate, number of stop bits, even or odd parity, interrupt mode, and receiver or transmitter enable. the parameters are loaded to the appropriate write buffer becoming empty transmit interrupt external status interrupt break/abort detection tx underrun/eom sync transition cts transition dcd transition z80-sio interrupt interrupt on first character valid address byte (sdlc) first non-sync character (sync) first data character end-of-frame (sdlc) framing error receive overrun error parity error special receive condition interrupt receive character interrupt on all receive characters receive interrupt
z80 cpu peripherals user manual um008101-0601 serial input/output 231 registers by the system program. wr4 parameters must be issued before wr1, wr3, and wr5 parameters or commands. if the data is transmitted over a modem or rs232c interface, the request to send (rts ) and data terminal ready (dtr ) outputs must be set along with the transmit enable bit. transmission cannot begin until the transmit enable bit is set. the auto enables feature allows the programmer to send the first data character of the message to the z80 sio without waiting for cts .ifthe auto enables bit is set, the z80 sio waits for the cts pintogolow before it begins data transmission. cts ,dcd , and sync are general- purpose i/o lines that may be used for functions other than their labeled purposes. if cts is used for another purpose, the auto enables bit must be programmed to 0. figure 111 illustrates asynchronous message formats; table 3 describes wr3, wr4, and wr5 with bits set to indicate the applicable modes, parameters and commands in asynchronous modes. wr2 (channel b only) stores the interrupt vector; wr1 defines the interrupt modes and data transfer modes. wr6 and wr7 are not used in asynchronous modes. table 4 describes the typical program steps that implement a full-duplex receive/transmit operation in either channel. figure 111. asynchronous message format marking line start d0 d1 dn n = 5, 6, 7, or 8 message flow may be present or not even or odd parity stop marking line 1, 1 1/2, or 2 bits asynchronous format all transactions occur on a falling edge of txc

um008101-0601 serial input/output 232 asynchronous transmit the transmit data output (txd) is held marking (high) when the trans- mitter has no data to send. under program control, the send break (wr5, d4) command can be issued to hold txd spacing (low) until the command is cleared. the z80 sio automatically adds the start bit, the programmed parity bit (odd, even, or no parity), and the programmed number of stop bits to the data character to be transmitted. when the character length is six or seven bits, the unused bits are automatically ignored by the z80 sio. if the char- acter length is five bits or less, refer to the table in the write register 5 description (z80 sio programming section) for the data format. serial data is shifted from txd at a rate equal to 1, 1/16th, 1/32nd, or 1/64th of the clock rate supplied to the transmit clock input txc serial data is shifted out on the falling edge of txc . if set, the external/status interrupt mode monitors the status of dcd ,cts , and sync throughout the transmission of the message. if these inputs change for a period of time greater than the minimum specified pulse width, the interrupt is generated. in a transmit operation, this feature is used to monitor the modem control signal cts . table 3. contents of write registers 3, 4, and 5 in asynchronous modes bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wr3 00=rx5bits/char 10 = rx 6 bits/char 01 = rx 7 bits/char 11=rx8bits/char auto enables 00 0 0 rx enable wr4 00 = x1 clock mode 01 = x16 clock mode 10 = x32 clock mode 11 = x64 clock mode 0000=notused 01 = 1 stop bit/char 10 = 1-1/2 stop bits/ char 11 = 2 stop bits/char even/ odd parity parity enable
z80 cpu peripherals user manual um008101-0601 serial input/output 233 wr5 dtr 00 = tx 5 bits (or less)/ char 10 = tx 6 bits/char 01 = tx 7 bits/char 11=tx8bits/char send break tx enable 0rts0 table 4. asynchronous mode function typical program steps comments register: information loaded: initialize wr0 channel reset reset sio wr0 pointer 2 wr2 interrupt vector channel b only wr0 pointer 4, reset external/status interrupt wr4 asynchronous mode, parity information, stop bits information, clock rate information issue parameters wr0 pointer 3 wr3 receive enable, auto enables, receive character length wr0 pointer 5 table 3. contents of write registers 3, 4, and 5 in asynchronous modes (continued) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

um008101-0601 serial input/output 234 wr5 request to send, transmit enable, transmit character length, data terminal ready receive and transmit both fully initialized. auto enables enables transmitter if cts is active and receiver if dcd is active wr0 pointer 1, reset external/status interrupt wr1 transmit interrupt enable, status affects ve c t o r, interrupt on all receive characters. disable wait/ready function, external interrupt enable transmit/receive interrupt mode selected. external interrupt monitors the status of the cts ,dcd ,and sync inputs and detects the break sequence. status affects vector in channel b only. this data byte must be transferred or no transmit interrupts occur. transfer first data byte to sio idle mode execute halt instruction or other program program is waiting for an interrupt from the sio data transfer and error monitoring z80 interrupt acknowledge cycle transfers rr2 to cpu when the interrupt occurs, the interrupt vector is modified by: 1) receive character available; 2) transmit buffer empty; 3) external/status change; and 4) special receive condition. if a character is received: ? transfer data character to cpu ? update pointers and parameters ? return from interrupt if transmitter buffer is empty: program control is transferred to one of the eight interrupt service routines. ? transfer data character to sio ? update pointers and parameters ? return from interrupt table 4. asynchronous mode (continued) function typical program steps comments
z80 cpu peripherals user manual um008101-0601 serial input/output 235 asynchronous receive an asynchronous receive operation begins when the receive enable bit is set. if the auto enables option is selected, dcd must be low. a low (spacing) condition on the receive data input (rxd) indicates a start bit. if this low persists for at least one-half of a bit time, the start bit is assumed to be valid and the data input is then sampled at mid-bit time until the entire character is assembled. this method of detecting a start bit improves error rejection when noise spikes exist on an otherwise marking line. if the x1 clock mode is selected, bit synchronization must be accom- plished externally. receive data is sampled on the rising edge of rxc. the receiver inserts 1s when a character length of other than eight bits is if external status changes: if used with processors other than the z80, the modified interrupt vector (rr2) should be returned to the cpu in the interrupt acknowledge sequence. ? transfer rrd to cpu ? perform error routines (include break detection) ? return from interrupt if special receive condition occurs: ? transferrr1tocpu ? d6 special error (such as framing error) routine ? return from interrupt termination redefine receive/transmit interrupt modes disable transmit/receive modes when transmit or receive data transfer is complete. update modem control outputs (such as rts off) in transmit, the all sent status bit indicates transmission is complete. table 4. asynchronous mode (continued) function typical program steps comments

um008101-0601 serial input/output 236 used. if parity is enabled, the parity bit is not stripped from the assembled character for character lengths other than eight bits. for lengths other than eight bits, the receiver assembles a character length of the required number of data bits, plus a parity bit and is for any unused bits. for example, the receiver assembles a 5-bit character with the following format: 11 p d4 d3 d2 d1 d0. because the receiver is buffered by three 8-bit registers in addition to the receive shift register, the cpu has enough time to service an interrupt and to accept the data character assembled by the z80 sio. the receiver also has three buffers that store error flags for each data character in the receive buffer. these error flags are loaded at the same time as the data characters. after a character is received, it is checked for the following error conditions: when parity is enabled, the parity error bit (rr1, d4) is set whenever the parity bit of the character does not match with the programmed parity. once this bit is set, it remains set until the error reset command (wr0) is given. the framing error bit (rr1, d6) is set if the character is assembled without any stop bits (that is, a low level detected for a stop bit). unlike the parity error bit, this bit is set (and not latched) only for the character on which it occurred. detection of framing error adds an additional one-half of a bit time to the character time so the framing error is not interpreted as a new start bit. if the cpu fails to read a data character while more than three characters have been received, the receive overrun bit rr1 d5) is set. when this occurs, the fourth character assembled replaces the third character in the receive buffers. with this arrangement, only the character that has been written over is flagged with the receive overrun error bit. like parity error, this bit can only be reset by the error reset command from the cpu. both the framing error and receive overrun error cause an interrupt with the interrupt vector indicating a special receive cond ition (if status affects vector is selected).
z80 cpu peripherals user manual um008101-0601 serial input/output 237 after the parity error and receive overrun error flags are latched, the error status that is read indicates an error in the current word in the receive buffer plus any parity or overrun errors received after the last error reset command. to keep correspondence between the state of the error buffers and the contents of the receive data buffers, the error status register must be read before the data. this is easily accomplished if vectored interrupts are used, because a special interrupt vector is generated for these conditions. while the external/status interrupt is enabled, break detection causes an interrupt and the break detected status bit (rr0, d7) is set. the break detected interrupt should be responded to by issuing the reset external/ status interrupt command to the z80 sio in response to the first break detected interrupt that has a break status of 1 (rr0, d7). the z80 sio monitors the receive data input and waits for the break sequence to terminate, at which time the z80 sio interrupts the cpu with the break status set to 0. the cpu must again issue the reset external/status inter- rupt command in its interrupt service routine to reinitialize the break detection logic. the external/status interrupt also monitors the status of dcd .ifthedcd pin becomes inactive for a period greater than the minimum specified pulse width, an interrupt is generated with the dcd status bit (rr0, d3) set to 1. the dcd input is inverted in the rr0, status register. if the status is read after the data, the error data for the next word is also included if it has been stacked in the buffer. if operations are performed rapidly enough so the next character is not yet r eceived, the status register remains valid. an exception occurs when the interrupt on first character only mode is selected. a special interrupt in this mode holds the error data and the character itself (even if read from the buffer) until the error reset command is issued. this interrupt prevents further data from becoming available in the receiver until the reset command is issued, and allows cpu intervention on the character with the error even if dma or block transfer techniques are in use. if interrupt on every character is selected, the interrupt vector is different an error status occurs in rr1. if a receiver overrun occurs, the most recent

um008101-0601 serial input/output 238 character received is loaded into the buffer; the character preceding it is lost. when the character that has been written over the other characters is read, the receive overrun bit is set and the special receive. condition vector is returned if status affects vector is enabled. in a polled environment, the receive character available bit (rr0, d0) must be monitored so that the z80 cpu knows when to read a character. this bit is automatically reset when the receive buffers are read. to prevent overwriting data in polled operations, the transmit buffer status must be cheeked before writing to the transmitter. the transmit buffer empty bit is set to 1 whenever the transmit buffer is empty. synchronous operation overview before describing synchronous transmission and reception, the three types of character synchronization, monosync, bisync, and external sync, require explanation. these modes use the x1 clock for both transmit and receive operations. data is sampled on the rising edge of the receive clock input (rxc ). transmitter data transitions occur on the falling edge of the transmit clock input (txc ). the differences between monosync, bisync, and external sync are in the form in which initial character synchronization is achieved. the mode of operation must be selected before sync characters are loaded, because the registers are used differently in the various modes. figure 112 depicts the formats for all three of these synchronous modes.
z80 cpu peripherals user manual um008101-0601 serial input/output 239 figure 112. synchronous formats message flow beginning beginning beginning (a) monosync message format (internal sync detected) (b) bisync message format (internal sync detected) (c) external sync detect format 07 07 07 70 70 70 15 8 15 8 15 8 data field crc character crc character #1 #2 #1 #2 #1 #2 #1 #2 sync character sync character sync character crc character crc character crc character crc character data field data field

um008101-0601 serial input/output 240 synchronous modes of operation monosync in a receive operation, matching a single sync character (8-bit sync mode) with the programmed sync character stored in wr7 implies char- acter synchronization and enables data transfer. bisync matching two contiguous sync characters (16-bit sync mode) with the programmed sync characters stored in wr6 and wr7 implies character synchronization. in both the monosync and bisync modes, sync is used as an output, and is active for the part of the receive clock that detects the sync character. external sync in this mode, character synchronization is established externally. sync is an input that indicates external character synchronization has been achieved. after the sync pattern is detected, the external logic must wait for two full receive clock cycles to activate the sync input. the sync input must be held low until character synchronization is lost. character assembly begins on the rising edge of rxc that precedes the falling edge of sync . in all cases after a reset, the receiver is in the hunt phase, during which the z80 sio looks for character synchronization. the hunt can begin only when the receiver is enabled, and data transfer can begin only when char- acter synchronization has been achieved. if character synchronization is lost, the hunt phase can be re-entered by writing a control word with the enter hunt phase bit set (wr3, d4). in the transmit mode, the trans- mitter always sends the programmed number of sync bits (8 or 16). in the
z80 cpu peripherals user manual um008101-0601 serial input/output 241 monosync mode, the transmitter transmits from wr6; the receiver compares against wr7. in the monosync, bisync, and external sync modes, assembly of received data continues until the z80 sio is reset, or until the receiver is disabled (by command or by dcd in the auto enables mode), or until the cpu sets the enter hunt phase bit. after initial synchronization has been achieved, the operation of the mono- sync, bisync, and external sync modes is similar. any differences are spec- ified in the following text. table 5 describes how wr3, wr4, and wr5 are used in synchronous receive and transmit operations. wr0 points to other registers and issues various commands, wr1 defines the interrupt modes, wr2 stores the interrupt vector, and wr6 and wr7 store sync characters. table 6 illus- trates the typical program steps that implement a half-duplex bisync transmit operation. table 5. contents of write registers 3, 4, and 6 in synchronous modes bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 wr 3 00 = ax 5 bits/char 10 = rx 6 bits/char 01 = rx 7 bits/char 11=rx8bits/char auto enables enter hunt mode rx crc enable 0 sync char load inhibit rx enable wr 4 0 0 00 = 8-bit sync char 01 = 16-bit sync char 10 = sdlc mode 11 = ext sync mode 0 selects sync modes 0 selects sync modes even/odd parity parity enable wr 5 dtr 00=tx5bits(orless)/ char 10 = tx 6 bits/char 01 = tx 7 bits/char 11 = tx 8 bits/char send break tx enable 1 selects crc-16 rts tx crc enable

um008101-0601 serial input/output 242 table6.bisynctransmitmode function typical program steps comments register information loaded initialize wr0 channel reset, reset transmit crc generator reset sio, initialize crc generator wr0 pointer 2 wr2 interrupt vector channel b only wr0 pointer 3 wr3 auto enables transmission begins only after cts is detected wr0 pointer 4 wr4 parity information, sync modes information, x1clock mode issue transmit parameters wr0 pointer 6 wr6 sync character 1 wr0 pointer 7, reset external/status interrupts wr7 sync character 2 wr0 pointer 1, reset external/status interrupts wr1 status affects vector, external interrupt enable, transmit interrupt enable or wait/ready mode enable external interrupt mode monitors the status of cts and dcd input pins as well as the status of tx underrun/eom latch. transmit interrupt enable interrupts when the transmit buffer becomes empty; the wait/readymodecanbeusedto transfer data using dma or cpu block transfer.
z80 cpu peripherals user manual um008101-0601 serial input/output 243 wr0 pointer 5 status affects vector (channel b only). transmit crc enable should be set when first non-sync data is sent to z80 sio. need several sync characters in the beginning of message. transmitter is fully initialized. wr5 request to send, transmit enable, bisync crc, transmit character length first sync byte to sio idle mode execute halt instruction or some other program waiting for interrupt or wait/ ready output to transfer data. data transfer and status monitoring when interrupt (wait/ready) occurs: interrupt occurs (wait/ready becomes active) when first data byte is being sent, wait mode allows cpu block transfer from memory to sio; ready mode allows dma block transfer from memory to sio. the dma chip can be programmed to capture special control characters (by examining only the bits that specify ascii or ebcdic control characters), and interrupt cpu. ? include/exclude data byte from crc accumulation (in sio) ? transfer data byte from cpu (or memory) to sio ? detect and set appropriate flags for control characters (in cpu) ? reset tx underrun/eom latch wr0 if last character of message is detected ? update pointers and parameters (cpu) return from interrupt if error condition or status change occurs: tx underrun/eom indicates either transmit underrun (sync character being sent) or end of message (crc- 16 being sent). ? transfer rr0 to cpu ? execute error routine ? return from interrupt termination redefine interrupt modes, update modem control outputs (for example, turn off rts ) program should gracefully terminate message disable transmit mode table 6. bisync transmit mode (continued) function typical program steps comments

um008101-0601 serial input/output 244 synchronous transmit initialization the system program must initialize the transmitter with the following parameters: odd or even parity, x1 clock mode, 8-bit or 16-bit sync char- acter(s), crc polynomial, transmitter enables, request to send, data terminal ready, interrupt modes, and transmit character length. wr4 parameters must be issued before wr1, wr3, wr5, wr6, and wr7 parameters or commands. one of two polynomials, crc -16(x 16 +x 15 +x 2 +1)orsdlc(x 16 + x 12 +x 5 + 1), may be used with synchronous modes. in either case (sdlc mode not selected), the crc generator and checker are reset to all 0s. in the transmit initialization process, the crc generator is initialized by setting the reset transmit crc generator command bits (wr0). both the trans- mitter and the receiver use the same polynomial. transmit interrupt enable or wait/ready enable can be selected to transfer the data. the external/status interrupt mode is used to monitor the status of the clear to send (cts ) input as well as the transmit underrun/eom latch. optionally, the auto enables feature can be used to enable the trans- mitter when cts is active. the first data transfer to the z80 sio can begin when the external/status interrupt occurs (cts status bit set) or immediately following the transmit enable command (if the auto enables modes is set). transmit data is held marking after reset or if the transmitter is not enabled. break may be programmed to generate a spacing line that begins as soon as the send break bit is set. with the transmitter fully initialized and enabled, the default condition is continuous transmission of the 8-bit or 16-bit sync character. data transfer and status monitoring
z80 cpu peripherals user manual um008101-0601 serial input/output 245 in this phase, there are several combinations of data transfers using inter- rupts and wait/ready status. data transfer using interrupts if the transmit interrupt enable bit (wr1, d1) is set, an interrupt is gener- ated each time the transmit buffer becomes empty. the interrupt can be satisfied either by writing another character to the transmitter or by reset- ting the transmitter interrupt pending latch with a reset transmitter pending command (wr0, cmd5). if the interrupt is satisfied with this command and nothing more is written to the transmitter, there can be no further transmit buffer empty interrupts, because it is the process of the buffer becoming empty that causes the interrupts and the buffer cannot become empty when it is already empty. this situation does cause a transmit underrun condition, which is explained in the ? ? bisync transmit underrun ? on page 245 ? section. data transfer using wait /ready to the cpu, the activation of wait indicates that the z80 sio is not ready to accept data and that the cpu must extend the output cycle. to a dma controller, ready indicates that the transmit buffer is empty and that the z80 sio is ready to accept the next data character. if the data character is not loaded to the z80 sio by the time the transmit shift register is empty, the z80 sio enters the transmit underrun condition. bisync transmit underrun in bisync protocol, filler characters are inserted to maintain synchroniza- tion when the transmitter has no data to send (transmit underrun condi- tion). the z80 sio has two programmable options for resolving this situation: it can insert sync characters, or it can send the crc characters generated so far, followed by sync characters. these options are under the control of tile reset transmit underrun/eom command in wr0. following a chip or channel reset, the transmit underrun/eom status bit (rr0, d6) is in a set condition and allows the

um008101-0601 serial input/output 246 insertion of sync characters when there is no data to send. crc is not calculated on the automatically inserted sync characters. when the cpu detects the end of message, a reset transmit underrun/eom command can be issued. this action allows crc to be sent when the transmitter has no data. in this case, the z80 sio sends crc, followed by sync charac- ters, to terminate the message. there is no restriction as to when in the message the transmit underrun/ eom bit can be reset. if reset is issued after the first data character has been loaded, the 16-bit crc is sent and followed by sync characters the first time the transmitter has no data to send. because of the transmit underrun condition, an external/status interrupt is generated whenever the transmit underrun/eom bit becomes set. in the case of sync insertion, an interrupt is generated only after the first automatically inserted sync character has been loaded. the status indicates the transmit underrun/ eom bit and the transmit buffer empty bit are set. in the case of crc insertion, the transmit underrun/eom bit is set and the transmit buffer empty bit is reset while crc is being sent. when crc has been completely sent, the transmit buffer empty status bit is set and an interrupt is generated to indicate to the cpu that another message can begin (this interrupt occurs because crc has been sent and sync has been loaded). if no more messages are to be sent, the program can terminate transmission by resetting rts, and disabling the transmitter (wr5, d3). pad characters may be sent by setting the z80 sio to eight bits/transmit character and writing ff to the transmitter while sending crc. alterna- tively, the sync characters can be redefined as pad characters during this time. the following example clarifies this point. 1. the z80 sio interrupts with the transmit buffer empty bit set. 2. the cpu recognizes that the last character (etx) of the message has already been sent to the z80 sio by examining the internal program status.
z80 cpu peripherals user manual um008101-0601 serial input/output 247 3. toforcethez80siotosendcrc,thecpuissuesthereset transmit underrun/eom latch command (wr0) and satisfies the interrupt with the reset transmit interrupt pending command. (this command prevents the z80 sio from requesting more data.) because of the transmit underrun caused by this command, the z80 sio starts sending crc. the z80 sio also causes an external/status interrupt with the transmit underrun/eom latch set. 4. the cpu satisfies this interrupt by loading pad characters to the transmit buffer and issuing the reset external/status interrupt command. 5. with this sequence, crc is followed by a pad character instead of a sync character. the z80 sio interrupts with a transmit buffer empty interrupt when crc is completely sent and that the pad character is loaded to the transmit shift register. 6. from this point on the cpu can send more pad characters or sync characters. bisync crc generation setting the transmit crc enable bit (wr5, d0) initiates crc accumula- tion when the program sends the first data character to the z80 sio. although the z80 sio automatically transmits up to two sync characters (18-bit sync), it is recommended to send a few more sync characters ahead of the message (before enabling transmit crc) to ensure synchronization at the receiving end. the transmit crc enable bit can be changed at any time in the message to include or exclude a particular data character from crc accumulation. the transmit crc enable bit should be in the suitable state when the data char- acter is loaded from the transmit data buffer to the transmit shift register. to ensure this bit is in a suitable state, the transmit crc enable bit must be issued before sending the data character to the z80 sio.

um008101-0601 serial input/output 248 transmit transparent mode transparent mode (bisync protocol) operation is made possible by the ability to change transmit crc enable on the fly and by the additional capability of inserting 16-bit sync characters. exclusion of idle characters from crc calculation can be achieved by disabling crc calculation immediately preceding the idle character transfer to the z80 sio. in the case of a transmit underrun condition in the transparent mode, a pair of dle-syn characters are sent. the z80 sio can be programmed to send the dle-syn sequence by loading a idle character to wr6 and a sync character to wr7. transmit termination the z80 sio is equipped with a special termination feature that maintains data integrity and validity. if the transmitter is disabled while a data or sync character is being sent, that character is sent as usual, but is followed by a marking line rather than crc or sync characters. when the transmitter is disabled, a character in the buffer remains in the buffer. if the transmitter is disabled while crc is being sent, the 16-bit transmission is completed, but sync is sent instead of crc. a programmed break is effective as soon as it is written to the control register; therefore, characters in the transmit buffer and shift register are lost. in all modes, characters are sent with the least-significant bits first. this requires right justification of transmitted data if the word length is less than eight bits. if the word length is five bits or less, the special technique described in the write register 5 discussion (z80 sio programming section) must be used for the data format. the states of any unused bits in a data character are irrelevant except when in the five bits or less mode. if the external/status interrupt enable bit is set, transmitter conditions such as ? starting to send crc characters, ?? starting to send sync characters, ? and cts changing state cause interrupts that have a unique vector if status affects vector is set. this interrupt mode may be used during block transfers.
z80 cpu peripherals user manual um008101-0601 serial input/output 249 all interrupts may be disabled for operation in a polled mode or to avoid interrupts at inappropriate tunes during the execution of a program. synchronous receive initialization the system program initiates the synchronous receive operation with the following parameters: odd or even parity, 8-bit or 16-bit sync characters, x1 clock mode, crc polynomial, receive character length, and more. sync characters must be loaded to registers wr6 and wr7. the receivers can be enabled only after all receive parameters are set. wr4 parameters must be issued before wr1, wr3, wr5, wr6, and wr7 parameters or commands. after these condititons are met, the receiver is in the hunt phase. it remains in this phase until character synchronization is achieved. under program control, all the leading sync characters of the message can be inhibited from loading the receive buffers by setting the sync character load inhibit bit in wr3. data transfer and status monitoring after character synchronization is achieved, the assembled characters are transferred to the receive data fifo. the following four interrupt modes are available to transfer the data and its associated status to the cpu. no interrupts enabled this mode is used for a purely polled operation or for off-line conditions. interrupt on first character only this mode is normally used to start a polling loop or a block transfer instruction using wait /ready to synchronize the cpu or the dma device to the incoming data rate. in this mode, the z80 sio interrupts on the first character and thereafter interrupts only if special receive condi-

um008101-0601 serial input/output 250 tions are detected. the mode is reinitialized with the enable interrupt on next receive character command to allow the next character received to generate an interrupt. parity errors do not cause interrupts in this mode, but end-of-frame (sdlc mode) and receive overrun do. if external/status interrupts are enabled, they may interrupt any time dcd changes state. interrupt on every character whenever a character enters the receive buffer, an interrupt is generated. error and special receive conditions generate a special vector if status affects vector is selected. optionally, a parity error may be directed not to generate the special interrupt vector. special receive condition interrupts the special receive condition interrupt can occur only if either the receive interrupt on first character only or interrupt on every receive character modes is also set. the special receive condition interrupt is caused by the receive overrun error condition. since the receive overrun and parity error status bits are latched, the error status-when read-reflects an error in the current word in the receive buffer in addition to any parity or overrun errors received after the last error reset command. these status bits can only be reset by the error reset command. crc error checking and termination a crc error check on the receive message can be performed on a per char- acter basis under program control. the receive crc enable bit (wr3, d3) must be set/reset by the program before the next character is transferred from the receive shift register to the receive buffer register. this ensures proper inclusion or exclusion of data characters in the crc check. to allow the cpu ample time to enable or disable the crc check on a particular character, the z80 sio calculates crc eight bit times after the character has been transferred to the receive buffer. if crc is enabled
z80 cpu peripherals user manual um008101-0601 serial input/output 251 before the next character is transferred, crc is calculated on the transferred character. if crc is disabled before the time of the next transfer, calcula- tion proceeds on the word in progress, but the word just transferred to the buffer is not included. when these requirements are satisfied, the 3-byte receive data buffer is, in effect, unusable in bisync operation. crc may be enabled and disabled as many times as necessary for a given calculation. in the monosync, bisync, and external sync modes, the crc/framing error bit (rr1, d6) contains the comparison result of the crc checker 16-bit times (eight bits delay and eight shifts for crc) after the character has been transferred from the receive shift register to the buffer. the result should be zero, indicating an error-free transmission. the result is valid only at the end of crc calculation. if the result is examined before this time, it usually indicates an error. the comparison is made with each transfer and is valid only as long as the character remains in the receive fifo. following is an example of the crc checking operation when four charac- ters (a, b, c, and d) are received in that order. character a loaded to buffer character b loaded to buffer if crc is disabled before c is in the buffer, crc is not calculated on b. character c loaded to buffer after c is loaded, the crc/framing error bit shows the result of the comparison through character a. character d loaded to buffer after d is in the buffer, the crc error bit shows the result of the comparison through character b whether or not b was included in the crc calculations. due to the serial nature of crc calculation, the receive clock (rxc ) must cycle 16 times (8-bit delay plus 8-bit crc shift) after the second note:

um008101-0601 serial input/output 252 crc character has been loaded to the receive buffer, or 20 times (the previous 16 plus 3-bit buffer delay and 1-bit input delay) after the last bit is at the rxd input, before crc calculation is complete. a faster external clock can be gated to the receive clock input to supply the required 16 cycles. the transmit and receive data path diagram (figure 109) illus- trates the various points of delay in the crc path. the typical program steps that implement a half-duplex bisync receive mode are illustrated in table 7. the complete set of command and status bit definitions are explained under ? programming ? on page 272 . table7.bisyncreceivemode function typical program steps comments register information loaded initialize wr0 channel reset, reset receive crc checker reset sio; initialize receive crc checker wr0 pointer 2 wr2 interrupt vector channel b only wr0 pointer 4 wr4 parity information, sync modes information, clock mode issue receive parameters wr0 pointer 5, reset external status interrupt wr5 bisync crc-16, data terminal ready wr0 pointer 3 wr3 sync character load inhibit, receive crc enable; enter hunt mode, auto enables, receive character length sync character load inhibit strips all the leading sync characters at the beginning of the message. auto enables enables the receiver to accept data only after the dcd input is active. wr0 pointer 6 wr6 sync character 1 wr0 pointer 7 wr7 sync character 2
z80 cpu peripherals user manual um008101-0601 serial input/output 253 wr0 pointer 1, reset external/status interrupt wr1 status affects vector, external interrupt enable, receive interrupt on first character only in this interrupt mode, only the first non-sync data character is transferred to the cpu. all subsequent data is transferred on a dma basis; however, special receive condition interrupts interrupt the cpu. status affects vector used in channel b only. wr0 pointer 3, enable interrupt on next receive character resetting this interrupt mode provides simple program loopback entry for the next transaction. wr3 receive enable, sync character load inhibit, enter hunt mode auto enable, receive word length wr3 is reissued to enable receiver; receive crc enable must be set after receiving soh or stx character. idle mode execute halt instruction or some other program receive mode is fully initialized and the system is waiting for interrupt on first character. table 7. bisync receive mode (continued) function typical program steps comments

um008101-0601 serial input/output 254 data transfer and status monitoring when interrupt on first character occurs, the cpu performs the following: during the hunt mode, the sio detects two contiguous characters to establish synchronization. the cpu establishes the dma mode and all subsequent data characters are transferred by the dma controller. the controller is also programmed to capture special characters (by examining only the bits that specify ascii or ebcdic control characters) and interrupt the cpu upon detection. in response, the cpu examines the status or control characters and takes appropriate action, such as crc enable update. ? transfers data byte to cpu ? detects and sets appropriate flags for control characters (in cpu) ? includes/excludes data byte in crc checker ? updates pointers and other parameters ? enables wait/ready for dma operation ? enables dma controller ? returns from interrupt when wait/ready becomes active, the dma controller performs the following: ? transfers data byte to memory ? interrupts cpu if a special character is captured by the dma controller ? interrupts the cpu if the last character of the message is detected for message termination, the cpu performs the following: the sio interrupts the cpu for error condition, and the error routine aborts the present message, clears the error condition, and repeats the operation. ? transfers rr1 to the cpu ? sets ack/nak reply flag based on crc result ? updates pointers and parameters ? returns from interrupt table 7. bisync receive mode (continued) function typical program steps comments
z80 cpu peripherals user manual um008101-0601 serial input/output 255 sdlc (hdlc) operation overview the z80 sio allows processing of both high-level synchronous data link control (hdlc) and ibm synchronous data link control (sdlc) protocols. in this chapter only synchronous data link control (sdlc) is covered because of the similarity between sdlc and hdlc. the sdlc mode is bit oriented which differs from synchronous bisync protocol, which is character oriented. therefore, sdlc mode allows trans- parent operation and variable message length. the bit-orientation sdlc is a flexible protocol because it can process longer message length and bit patterns. ibm document ga27-3093 has more information about sdlc protocol. the sdlc message, called the frame ( figure 113 ), is opened and closed by flags that are similar to the sync characters in bisync protocol. the z80 sio handles the transmission and recognition of the flag characters that mark the beginning and end of the frame. although the z80 sio can receive shared-zero flags, it cannot transmit them. the 8-bit address field of an sdlc frame contains the secondary station address. the z80 sio has an address search mode that recognizes the secondary station address, allowing it to accept or reject the frame. termination redefine interrupt modes and sync modes update modem controls disables receive mode table 7. bisync receive mode (continued) function typical program steps comments

um008101-0601 serial input/output 256 the control field of the sdlc frame is transparent to the z80 sio, and it is transferred to the cpu. the z80 sio handles the frame check sequence in a way that simplifies the program by incorporating features, such as initializing the crc generator to all 1s, resetting the crc checker when the opening flag is detected in the receive mode, and sending the frame check/flag sequence in the transmit mode. controller hardware is simplified by automatic zero insertion and deletion logic contained in the z80 sio. table 8 lists the contents of wr3, wr4, and wr5 during sdlc receive and transmit modes. wr0 points to other registers and issues commands. wr1 defines the interrupt modes. wr2 stores the interrupt vector. wr7 stores the flag character and wr6 the secondary address. figure 113. transmit/receive sdlc/hdlc message format sdlc transmit initialization the sdlc transmit mode must be initialized with the following parame- ters: sdlc mode, sdlc polynomial, request to send, data terminal ready, transmit character length, transmit interrupt modes (or wait/ready function), transmit enable, auto enables, and external/status interrupt. se ? sdlc transmit mode ? on page 262 ) selecting the sdlc mode and the sdlc polynomial allows the z80 sio to initialize the crc generator to all 1s. initialization is accomplished by issuing the reset transmit crc generator command wr0. refer to the beginning opening flag 0111 1110 address 8bits crc 15 #1 87 0 crc #2 closing flag 0111 1110 end message flow data field or i-field
z80 cpu peripherals user manual um008101-0601 serial input/output 257 ? synchronous operation ? on page 238 section for more details on the interrupt modes. after reset, or when the transmitter is not enabled, the transmit data output is held marking. break may be programmed to generate a spacing line. with the transmitter fully initialized and enabled, continuous flags are transmitted on the transmit data output. an abort sequence may be sent by issuing the send abort command wr0 cmd1). the send abort command causes at least 8, but less than 14, 1s to be sent before the line reverts to continuous flags. it is possible that the abort sequence (eight 1s) could follow up to five continuous 1 bits (allowed by the zero insertion logic) and thus cause up to thirteen 1s to be sent. any data being transmitted and any data in the transmit buffer is lost when an abort is issued. when required, an extra 0 is automatically inserted when five contiguous 1s occur in the data stream. automatic insertion does not apply to flags or aborts. data transfer and status monitoring sdlc mode allows several combinations of interrupts and wait/ready functions. data transfer using interrupts if the transmit interrupt enable bit is set, an interrupt is generated when the buffer becomes empty. the interrupt may be satisfied either by writing another character to the transmitter or by resetting the transmit interrupt pending latch with a reset transmitter pending command (wr0, cmd5). if the interrupt is satisfied with this command and no more is written to the transmitter, then no more transmitter interrupts occur. the result is a transmit underrun condition. when another character is written and sent, the transmitter can again become empty and interrupt the cpu. following the flags in an sdlc operation, the 8-bit address field, control field and

um008101-0601 serial input/output 258 information field may be sent to the z80 sio using the transmit interrupt mode. the z80 sio transmits the frame check sequence using the transmit underrun feature. when the transmitter is first enabled, it is already empty and cannot then become empty. therefore, no transmit buffer empty interrupts can occur until after the first data character is written. data transfer using wait/ready when the wait/ready function is selected, wait communicates to the cpu that the z80 sio is not ready to accept the data and that the cpu must extend the i/o cycle. to a dma controller, ready communicates that the transmitter buffer is empty and that the z80 sio is ready to accept the next character. if the data character is not loaded to the z80 sio by the time the transmit shift register is empty, the z80 sio enters the transmit underrun condition. address, control, and information fields may be transferred to table 8. contents of write registers 3, 4, and 5 in sdlc modes bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 wr 3 00 = rx 5 bits char 10 = rx 6 bits char 01 = rx 7 bits char 11 = rx 8 bits char auto enables enter hunt mode (if incoming data not needed) rx crc enable address search mode 0rx enable wr 4 00 1 selects sdlc mode 0 selects sdlc mode 0000 wr 5 dtr 00=tx5bits(orless) char 10=tx6bitschar 01=tx7bitschar 11 = tx 8 bits char 0 tx enable 0 selects sdlc crc rts tx crc enable
z80 cpu peripherals user manual um008101-0601 serial input/output 259 the z80 sio with this mode using the wait/ready function. the z80 sio transmits the frame check sequence using the transmit underrun feature. sdlc transmit underrun/end of message sdlc-like protocols do not have provisions for fill characters within a message. the z80 sio therefore automatically terminates an sdlc frame when the transmit data buffer and output shift register have no more bits to send. it does this by first sending the two bytes of crc followed by one or more flags. this technique allows very high-speed transmissions under dma or cpu block i/o control without requiring the cpu to respond quickly to the end of message condition. the z80 sio response to the underrun condition depends on the state of the transmit underrun/eom command. following a reset, the transmit underrun/eom status bit is in the set state and prevents the insertion of crc characters while there is no data to send. consequently, flag charac- ters are sent. the z80 sio starts sending the frame while data is written to thetransmitbuffer.betweenthetimethefirstdatabyteiswrittenandthe end of the message, the reset transmit underrun/eom command must be issued. thus the transmit underrun/eom status bit is in the reset state at the end of the message (when underrun occurs), which automatically sends the crc characters. the sending of crc again sets the transmit/underrun/ eom status bit. although there is no restriction about when the transmit underrun/eom bit can be reset within a message, the reset usually occurs after the first data character (secondary address) is sent to the z80 sio. resetting this bit allows crc and flags to be sent when there is no data to send, allowing additional time for the cpu to recognize the fault and respond with an abort command. by resetting this bit early in the message, the entire message is allotted the maximum amount of cpu response time in an unintentional transmit underrun situation. when the external/status interrupt is set and while crc is sent, the transmit underrun/eom bit is set and the transmit buffer empty bit is reset to indicate that the transmit register is full of crc data. when crc

um008101-0601 serial input/output 260 has been completely sent, the transmit buffer empty status bit is set and an interrupt is generated to indicate to the cpu that another message can begin. this interrupt occurs because crc is sent and the flag is loaded. if no more messages are to be sent, the program can terminate transmission by resetting rts , disabling the transmitter. in the sdlc mode, reset the transmit underrun/eom status bit immedi- ately after the first character is sent to the z80 sio. when the transmit underrun is detected, this ensures that the transmission time is filled by crc characters, giving the cpu enough time to issue the send abort command. this procedure also stops the flags from going on the line prematurely and eliminates the possibility of the receiver accepting the frame as valid data. for example, the data pattern, immediately preceding the automatic flag insertion, could match the crc checker, thereby giving a false crc check result. the external/status interrupt is generated when- ever the transmit underrun/eom bit is set as a result of the transmit underrun condition. the transmit underrun logic provides additional protection from premature flag insertion if the proper response is given to the z80 sio by the cpu interrupt service routine. the following example illustrates this point: 1. the z80 sio interrupts with the transmit buffer empty status bit set. 2. the cpu does not respond in a timely manner, which causes a transmit underrun condition. 3. the z80 sio starts sending crc characters (two bytes). 4. the cpu eventually satisfies the transmit buffer empty interrupt with a data character that follows the crc character being transmitted. 5. the z80 sio sets the external/status interrupt with the transmit underrun/eom status bit set 6. the cpu recognizes the transmit underrun/eom status and determines from its internal program status that the interrupt is not ? end of message ? .
z80 cpu peripherals user manual um008101-0601 serial input/output 261 7. the cpu immediately issues a send abort command wr0 to the z80 sio. 8. the z80 sio sends the abort sequence by destroying whatever data (crc, data, or flag) is being sent. as this sequence describes, the cpu has a protection of 22 minimum and 30 maximum transmit clock cycles. sdlc crc generation reset the crc generator to all 1s at the beginning of each frame before crc accumulation begins. actual accumulation begins when the program sends the address field (eight bits) to the z80 sio. although the z80 sio automatically transmits one flag character following the transmit enable, send a few more flag characters ahead of the message to ensure that char- acter synchronization occurs at the receiving end. synchronization is accomplished by externally timing out after enabling the transmitter, and before loading the first character. the transmit crc enable (wr5, d0) must be enabled before sending the address field. in the sdlc mode, all the characters between the opening and closing flags are included in crc accumulation, and the crc gener- ated in the z80 sio transmitter is inverted before it is sent on the line. transmit termination if the transmitter is disabled while a character is being sent, that character (data or flag) is sent, but is followed by a marking line rather than crc or flag characters. a character in the buffer while the transmitter is disabled, remains in the buffer; however, a programmed abort sequence executes when it is written to the control register. characters being transmitted, if any, are lost. in the case of crc, the 16-bit transmission is completed if the transmitter is disabled; however, flags are sent in place of crc.

um008101-0601 serial input/output 262 in all modes, characters are sent with the least-significant bits first. this requires right justification of data to be transmitted when the word length is less than eight bits. if the word length is five bits or less, use the special technique described in ? write register 5 ? on page 289 . because the number of bits/character can be changed on-the-fly, the data field can be filled with any number of bits. when used in conjunction with the receiver residue codes, the z80 sio can receive a message that has a variable i-field and retransmit it exactly as received with no previous infor- mation about the character structure of the i-field (if any). a change in the number of bits does not affect the character being shifted out. characters are sent with the number of bits programmed at the time that the character is loaded from the transmit buffer to the transmitter. if the external/status interrupt enable is set, transmitter conditions, such as ? startingtosendcrccharacters, ?? starting to send flag characters, ? and cts changing state, cause interrupts, having a unique vector if status affects vector is set. all interrupts can be disabled for operation in a polled mode. table 9 describes the typical program steps that implement the half-duplex sdlc transmit mode. table 9. sdlc transmit mode function typical program steps comments register information loaded: initialize wr0 channel reset reset sio wr0 pointer 2 wr2 interrupt vector channel b only wr0 pointer 3 wr3 auto enables transmitter sends data only after cts is detected wr0 pointer 4, reset external/status interrupts
z80 cpu peripherals user manual um008101-0601 serial input/output 263 wr4 parity information, sdlc mode, x1 clock mode wr0 pointer 1. reset external/status interrupts wr1 external interrupt enable, status affects vector, transmit interrupt enable or wait/ready mode enable the external interrupt mode monitors the status of the cts and dcd inputs, as well as the status of tx underrun/eom latch. transmit interrupt interrupts when the transmit butter becomes empty; the wait/ready mode canbeusedtotransferdataonadmaorblock transfer basis. the first interrupt occurs when cts becomes active, at which time flags are transmitted by the z80 sio. the first data byte (address field) can be loaded in the z80 sio after this interrupt. flags cannot be sent to the z80 sio as data. status affects vector used in channel b only. wr0 pointer 5 wr5 transmit crc enable, request to send, sdlc-crc transmit enable, transmit word length, data terminal ready sdlc-crc mode must be defined before initializing transmit crc generator wr0 reset transmit crc generator initialize crc generator to all 1s idle mode execute halt instruction or some other program waiting for interrupt or wait/ready output to transfer data table 9. sdlc transmit mode (continued) function typical program steps comments

um008101-0601 serial input/output 264 data transfer and status monitoring when interrupt (wait ready) occurs, the cpu performs the following: flags are transmitted by the sio as soon as transmit enable is set and cts becomes active. the cts status change is the first interrupt that occurs and is followed by transmit buffer empty for subsequent transfers. word length can be changed on-the-fly for variable i-field length. the data byte can contain address, control, or i- field information, but not a flag. reset tx underrun/eom latch in the beginning of the message to avoid a false end-of-frame detection at the receiving end. this ensures that, when underrun occurs, crc is transmitted and underrun interrupt (tx underrun/eom latch active) occurs. send abort can be issued to the sio in response to any interrupting, continuing to abort the transmission. ? changes transmit word length (if necessary) ? transfers data byte from cpu (memory) to sio ? resets tx underrun/eom latch wr0 if the last character of the i- field is sent, the sio performs the following: ? sends crc ? sends closing flag ? interrupts cpu with buffer empty status the cpu performs the following: ? issues reset tx interrupt pending command to the z80 sio ? updates ns count ? repeats the process for next message, and more. if the vector indicates an error, the cpu performs the following: ? sends abort ? executes error routine ? updates parameters, modes, and more table 9. sdlc transmit mode (continued) function typical program steps comments
z80 cpu peripherals user manual um008101-0601 serial input/output 265 sdlc receive initialization the system initializes the sdlc receive mode using polynomial, receive word length, and more. the flag characters must also be loaded in wr7 and the secondary address field loaded in wr6. the receiver is enabled only after all the receive parameters have been set. after all this is completed, the receiver is in the hunt phase and remains in this phase until the first flag is received. while in the sdlc mode, the receiver never re-enters the hunt phase, unless specifically instructed to do so by the program. the wr4 parameters must be issued prior to the wr1, wr3, wr5, wr6, and wr7 parameters. under program control, the receiver can enter the address search mode. if the address search bit (wr1, d2) is set, a character following the flag (first non-flag character) is compared to the programmed address in wr6 and the hardwired global address ( 1111 1111 ). if the sdlc frame address field matches either address, data transfer begins. because the z80 sio is capable of matching only one address character, extended address field recognition must be done by the cpu. in this instance, the z80 sio transfers the additional address bytes to the cpu as if they were data characters. if the cpu determines that the frame does not have the correct address field, it can set the hunt bit, and the z80 sio suspends reception and searches for a new message headed by a flag. termination redefine interrupt modes terminate gracefully update modem control outputs disable transmit mode table 9. sdlc transmit mode (continued) function typical program steps comments

um008101-0601 serial input/output 266 because the control field of the frame is transparent to the z80 sio, it is transferred to the cpu as a data character. extra zeros inserted in the data stream are automatically deleted; flags are not transferred to the cpu. data transfer and status monitoring after receipt of a valid flag, the assembled characters are transferred to the receive data fifo. the following four interrupt modes are available to transfer this data and its associated status. no interrupts enabled this mode is used for purely polled operations or for off-line conditions. interrupt on first character only use this mode to start a software polling loop or a block transfer instruc- tion using wait /ready to synchronize the cpu or fnma device to the incoming data rate. in this mode, the z80 sio interrupts on the first char- acter and thereafter only interrupts if special receive conditions are detected. the mode is reinitialized by the enable interrupt on next receive character command. the first character received after this command is issued causes an inter- rupt. if external/status interrupts are enabled, they may interrupt any time the dcd input changes state. special receive conditions such as end-of- frame and receiver overrun also cause interrupts. the end-of-frame inter- rupt can be used to exit the block transfer mode. interrupt on every character an interrupt is generated whenever the receive fifo contains a character. error and special receive conditions generate a special vector if status affects vector is selected.
z80 cpu peripherals user manual um008101-0601 serial input/output 267 special receive condition interrupts the special receive cond ition interrupt is not, as such, a separate interrupt mode. before the special receive condition can cause an interrupt, either interrupt on first receive character only or interrupt on every character must be selected. the special receive condition interrupt is caused by a receive overrun or end-of-frame detection. when the receive overrun status bit is latched, the error status read indicates that an error occurred in the current word in the receive buffer in addition to any errors received after the last error reset command. the receive overrun status bit can only be reset by the error reset command. the end-of-frame status bit indicates that a valid ending flag has been received and that the crc error and residue codes are also valid. character length may be changed on-the-fly. if the address and control bytes are processed as 8-bit characters, the receiver may be switched to a shorter character length while the first information character is being assembled. this change must be made fast enough so that it is effective before the number of bits specified for the character length have been assembled. for example, if the change is to be from the 8-bit control field to a 7-bit information field, the change must be made before the first seven bits of the i-field are assembled. sdlc receive crc checking control of the receive crc checker is automatic. it is reset by the leading flag and crc is calculated up to the final flag. the byte that has the end-of- frame bit set is the byte that contains the result of the crc check. if the crc/framing error bit is not set, the crc indicates a valid message. a special check sequence is used for the sdlc check because the transmitted crc check is inverted. the final check must be 0001 1101 0000 1111 . the 2-byte crc check characters must be read by the cpu and discarded because the z80 sio, while using them for crc checking, treats them as ordinary data.

um008101-0601 serial input/output 268 sdlc receive termination if enabled, a special vector is generated when the closing flag is received. this signals that the byte with the end-of-frame bit set has been received. in addition to the results of the crc check, rr1 has three bits of residue code valid at this time. when the number of bits in the i-field is not an inte- gral multiple of the character length used, these bits indicate the boundary between the crc check bits and the i-field bits. for a detailed description of the meaning of these bits, see the description of the residue codes in rr1 in ? z80 sio programming. ? any frame can be prematurely aborted by an abort sequence. aborts are detected if seven or more 1s occur, causing an external/status interrupt (if enabled) with the break/abort bit in rr0 set. after the reset external/ status interrupts command has been issued, a second interrupt occurs when the continuous 1s condition has been cleared. this can be used to distin- guish between the abort and idle line conditions. unlike the synchronous mode, crc calculation in sdlc does not have an 8-bit delay because all the characters are included in crc calculation. when the second crc character is loaded to the receive buffer, crc calcu- lation is complete. table 10 lists steps employed to implement a half-duplex sdlc receive mode. the complete set of command and status bit definitions is provided in the next section. table 10. sdlc receive mode function typical program steps comments register information loaded: initialize wr0 channel 2 reset sio wr0 pointer 2 wr2 interrupt vector channel b only wr0 pointer 4
z80 cpu peripherals user manual um008101-0601 serial input/output 269 wr4 parity information, sync mode, sdlc mode, x1 clock mode wr0 pointer 5, reset external/status interrupts wr5 sdlc-crc, data terminal ready wr0 pointer 3 wr3 receive crc enable, enter hunt mode, auto enables, receive character length, address search mode auto enables enables the receiver to accept data only after mb becomes active. address search mode enables sio to match the message address with the programmed address or the global address. wr0 pointer 6 wr6 secondary address field this address is compared to the message address in an sdlc poll operation. wr0 pointer 7 wr7 sdlcflag01111110 thisflagdetectsthestartandend-of- frame in an sdlc operation. in this interrupt mode, only the address field (1 character only) is transferred to the cpu. all subsequent fields (control, information, and more.) are transferred on a dma basis. status affects vector in channel b only. wr0 pointer 1, reset external/status interrupts wr1 status affects vector, external interrupt enable, receive interrupt on first character only. wr0 pointer 3, enable interrupt on next receive character this flag provides simple loop-back entry point for next transaction. wr3 receive enable, receive crc enable, enter hunt mode, auto enables, receiver character length, address search mode wr3 reissued to enable receiver. table 10. sdlc receive mode (continued) function typical program steps comments

um008101-0601 serial input/output 270 idle mode execute halt instruction or some other program sdlcreceivemodeisfully initialized and sio is waiting for the opening flag followed by a matching address field to interrupt the cpu. data transfer and status monitoring when interrupt on first character occurs, the cpu performs the following: during the hunt phase, the sio interrupts when the programmed address matches the message address. the cpu establishes the dma mode and all subsequent data characters are transferred by the dma controller to memory. ? transfers data byte (address byte) to cpu ? detects and sets appropriate flag for extended address field ? updates pointers and parameters ? enables dma controller ? enableswait/readyfunctioninsio ? returns from interrupt when the ready output becomes active, the dma controller performs the following: during the dma operation, the sio monitors the dcd input and the abort sequence in the data stream to interrupt the cpu with external status error. the special receive condition interrupt is caused by the receive overrun error. ? transfers the data byte to memory ? updates the pointers table 10. sdlc receive mode (continued) function typical program steps comments
z80 cpu peripherals user manual um008101-0601 serial input/output 271 when end of frame interrupt occurs, the cpu performs the following: detection of end-of-frame (flag) causes interrupt and deactivates the wait/ready function. residue codes indicate the bit structure of the last two bytes of the message that were transferred to memory under dma. 'error reset' is issued to clear the special condition. abort sequence is detected when seven or more 1s occur in the data stream. ? exits dma mode (disables wait/ ready) ? transfers rr1 to the cpu ? checks the crc error bit status and residue codes ? updates nr count ? issues error reset command to sio when abort sequence detected interrupt occurs, the cpu performs the following: ? transfers rr0 to the cpu ? exits dma mode ? issues the reset external status interrupt command to the sio ? enters the idle mode cpu is waiting for abort sequence to terminate. termination clears the break/abort status bit and causes interrupt. at this point, the program proceeds to terminate this message. when the second abort sequence interrupt occurs, the cpu performs the following: ? issues the reset external status interrupt command to the sio termination redefine interrupt modes, sync mode and sdlc modes, disable receive mode table 10. sdlc receive mode (continued) function typical program steps comments

um008101-0601 serial input/output 272 programming overview to program the z80 sio, the system program first issues a series of commands that initialize the basic mode of operation and then other commands that qualify conditions within the selected mode. for example, the asynchronous mode, character length, clock rate, number of stop bits, even or odd parity are first set, then the interrupt mode and, finally, receiver or transmitter enable. the wr4 parameters must be issued before any other parameters are issued in the initialization routine. both channels contain command registers that must be programmed via the system program prior to operation. the channel select input (b/a ) and the control/data input (c/d )arethe command structure addressing controls, and are normally controlled by the cpu address bus (see table 11). figures 114 through 117 illustrate the timing relationships for programming the write registers, and transferring data and status. write registers the z80 sio contains eight registers (wr7-wr0) in each channel that are programmed separately by the system program to configure the functional table 11. channel select functions c/ d b/ a function 00channeladata 01channelbdata 1 0 channel a commands/status 1 1 channel b commands/status
z80 cpu peripherals user manual um008101-0601 serial input/output 273 characteristics of the channels. with the exception of wr0, programming the write registers requires two bytes. the first byte contains three bits (d2- d0) that point to the selected register; the second byte is the actual control word that is written into the register to configure the z80 sio. after pointing to the selected register, a programmer can either read to test the read register or write to initialize the write register. the z80 sio software can be initialized in either a modular or structured mode, allowing the programmer to use powerful block i/o instructions. wr0 functions as a unique register because all the basic commands (cm02-cmdo) can be accessed with a single byte. reset (internal or external) initializes the pointer bits d0-d2 to point to wr0. the basic commands (cmd2-cmd0) and the crc controls (crc0, crc1) are contained in the first byte of any write register access. this allows maximum flexibility and system control. each channel contains the following control registers. these registers are addressed as commands, not data. write register 0 wr0, ( figure 114 ) is the command register; however, it is also used for crc reset codes and points to the other registers. table12.writeregister0 d7 d6 d5 d4 d3 d2 d1 do crc crc cmd cmd cmd ptr ptr ptr resetreset210210 code code 10

um008101-0601 serial input/output 274 figure 114. write register 0 pointer bits (d2-d0) bits d2-d0 are pointer bits that determine which write register the next byte writes to or which read register the next byte reads from. the first byte written to each channel after a reset (either by a reset command or by the external reset input) goes to wr0. following a read or write to any register (except wr0), the pointer points to wr0 command bits (d5-d3) threebits,d5-d3,areencodedtoissuethesevenbasicz80sio commands ( table 13 ). 00 01 10 11 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 null code reset rx crc checker reset tx crc generator reset tx underrun/eom latch register 0 register 1 register 2 register 3 register 4 register 5 register 6 register 7 null code send abort (sdlc) reset ext/status interrupts channel reset enable int on next ax character reset txint pending error reset return from int (ch-a only) d7 d6 d5 d4 d3 d2 d1 d0
z80 cpu peripherals user manual um008101-0601 serial input/output 275 command 0 (null). the null command has no effect. normally the null command instructs the z80 sio to wait while the pointers are set for the following byte. command 1 (send abort). this command is used only in sdlc mode to generate a sequence of eight to thirteen 1s. command 2 (reset external/status interrupts). after an external/status interrupt, such as a change on a modem line or a break condition, the status bits of rr0 are latched. this command re-enables them, again allowing interrupts to occur. latching the status bits captures short pulses until the cpu has time to read the change. command 3 (channel reset). this command performs the same function as an external reset, but on a single channel. channel a reset also resets the interrupt prioritization logic. all control registers for the channel must be rewritten after a channel reset command. after a z80 sio channel reset, add four system clock cycles before addi- tional commands or controls write to that channel. this is normally the same amount of time that is used by the cpu to fetch the next op code. table 13. z80 sio commands command cmd2 cmd1 cmd0 result 0 0 0 0 null command (no effect) 1 0 0 1 send abort (sdlc mode) 2 0 1 0 reset external/status interrupts 3 011channelreset 4 1 0 0 enable interrupt on next rx character 5 1 0 1 reset transmitter interrupt pending 6 1 1 0 error reset (latches 7 1 1 1 return from interrupt (channel a)

um008101-0601 serial input/output 276 command 4 (enable interrupt on next receive character). if the interrupt on first receive character mode is selected, command 4 reactivates the enable interrupt on next receive character mode after receiving each complete message. this sequence prepares the z80 sio for the next message. command 5 (reset transmitter interrupt pending). a transmitter interrupt occurs when the transmit buffer becomes empty. this interrupt happens only when the transmit interrupt enable mode is selected. when there are no more characters to be sent for example, at the end of message, issuing this command prevents further transmitter interrupts until after the next character is loaded to the transmit buffer or until crc is completely sent. command 6 (error reset). this command resets the error latches. parity and overrun errors are latched in rr1 until they are reset with this command. using this method, parity errors occurring in block transfers can be examined at the end of the block. command 7 (return from interrupt). this command must be issued in channel a and is interpreted by the z80 sio in the same way it interprets an reti command on the data bus. this command resets the interrupt under-service latch of the highest priority internal device under service. this reset allows lower-priority devices to interrupt through the daisy- chain. this command also allows use of the internal daisy-chain even in systems with no external daisy-chain or reti command. crc reset codes 0 and 1 (d6 and d7). used together, these bits select one of the three following reset commands, described in table 14 :
z80 cpu peripherals user manual um008101-0601 serial input/output 277 the reset transmit crc generator command normally initializes the crc generator to 0s. if the sdlc mode is selected, this command initializes the crc generator to 1s. the receive crc checker is also initialized to 1s for the sdlc mode. write register 1 wr1 ( figure 115 ) contains the control bits for the various interrupt and wait/ready modes. external/status interrupt enable (d0) the external/status interrupt enable allows interrupts to occur as a result of transitions on the dcd ,cts ,orsync inputs, as a result of a break/abort table 14. reset commands crc reset code 1 crc reset code 0 result 0 0 null code (no affect) 0 1 reset receive crc checker 1 0 reset transmit crc generator 1 1 reset tx underrun/end of message latch table15.writeregister1 d7 d6 d5 d4 wait/ready enable wait or ready function wait/ready on receive transmit receive interrupt mode 1 d3 d2 d1 d0 receive interrupt mode 0 status affects ve c t o r transmit interrupt enable external interrupts enable

um008101-0601 serial input/output 278 detection and termination, or at the beginning of crc or sync character transmission when the transmit underrun/eom latch sets. transmitter interrupt enable (d1) if enabled, interrupts occur whenever the transmitter buffer becomes empty. status affects vector (d2) this bit is active in channel b only. if this bit is not set, the fixed vector programmed in wr2 is returned from an interrupt acknowledge sequence. if this bit is set, the vector returned from an interrupt acknowledge is variable. table 16 describes the vector results. ta ble 17 describes the receive interrupt modes. receive interrupt modes 0 and 1 (d3 and d4) used together, these two bits specify the various character-available condi- tions. in receive interrupt modes 1, 2, and 3, a special receive condition can cause an interrupt that modifies the interrupt vector. table 16. vector results v3 v2 v1 result ch b 0 0 0 ch b transmit buffer empty 0 0 1 ch b external/status change 0 1 0 ch b receive character available 0 1 1 ch b special receive condition* ch a 1 0 0 ch a transmit buffer empty 1 0 1 ch a external/status change 1 1 0 ch a receive character available 1 1 1 ch a special receive condition* note: *special receive conditions: parity error, rx overrun error, framing error, end- of-frame (sdlc).
z80 cpu peripherals user manual um008101-0601 serial input/output 279 figure 115. write register 1 wait/ready function selection (d7-d5). the wait and ready functions are selected by controlling d5, d6, and d7. wait/ready function is enabled by setting wait/ready enable (wr1, d7) to 1. the ready function is selected by setting d5 (wait/ready function) to 1. if this bit is 1, the wait /ready output switches from high to low when the z80 sio is ready to transfer table 17. receive interrupt modes d4 receive interrupt mode 1 d3 receive interrupt mode 0result 0 0 receive interrupts disabled 0 1 receive interrupt on first character only 1 0 interrupt on all receive characters ? parity error is a special receive condition 1 1 interrupt on all receive characters ? parity error is not a special receive condition 00 01 10 11 rx int disable rx int on first character int on all rx characters (parity affects vector) int on all rx characters (parity does not affect vector) exe int enable tx int enable status affects vector (ch.b only) wait/ready on r/t wait /ready function wait/ready enable d7 d6 d5 d4 d3 d2 d1 d0 *or on special condition *

um008101-0601 serial input/output 280 data. the wait function is selected by setting d6 to 0. if this bit is 0, the wait /ready output is in the open-drain state and goes low when active. both the wait and ready functions can be used in either the transmit or receive modes, but not both simultaneously. if d5 (wait/ready on receive/ transmit) is set to 1, the wait/ready function responds to the condition of the receive buffer (empty or full). if d5 is set to 0, the wait/ready function responds to the condition of the transmit buffer (empty or full). the logic states of the wait /ready output, which are either active or inactive, depend on the combination of modes selected. table 18 summa- rizes these combinations. the wait output high-to-low transition occurs at the delay time tdic(wr) after the i/o request. the low-to-high transition occurs at the delay tdh (wr) at the falling edge of . the ready output high-to- low transition occurs at the delay tdl (wr) at the rising edge of .the ready output low-to-high transition occurs at the delay tdic(wr) after iorq falls. the ready function can occur when the z80 sio is not selected. when the ready output becomes active low, the dma controller issues table 18. wait/ready functions if d7 = 0 and d6 = 1 and d6 = 0 ready is high wait is floating if d7 = 0 and d5 = 0 and d5 = 1 ready is high when transmit buffer is full ready is high when receive buffer is empty wait is low when transmit buffer is full and s10dataportisanselected wait is low when receive buffer is empty and sid data port is selected ready is low when transmit buffer is empty ready is low when receive buffer is full wait is floating when transmit buffer is empty wait is floating when receive buffer is full
z80 cpu peripherals user manual um008101-0601 serial input/output 281 iorq and the corresponding s/a and c/d inputs to the z80 sio to transfer data. the ready output becomes inactive when iorq and cs become active. the ready function can occur internally in the z80 sio, whether it is addressed or not. therefore, the ready output becomes inactive when any cpu data or command transfer occurs. because the dma controller is not enabled when the cpu transfer occurs, the system continues to function normally. the wait function is active only when the cpu attempts to read z80 sio data that has not yet been received, which occurs frequently when block transfer instructions are used. the wait function can also become active (under program control) if the cpu tries to write data while the transmit buffer is still full. the wait output for either channel becomes active when the opposite channel is addressed. this active state occurs because the z80 sio is addressed and does not affect software loops or block move instructions. write register 2 wr2 ( figure 116 ) is the interrupt vector register and occurs in channel b only. v7-v4 and v0 are always returned exactly as written; v3-v1 are returned as written if the status affects vector (wr1, d2) control bit is 0. if this bit is 1, they are modified as explained in ? write register 1 ? on page 277 . table19.writeregister2interruptvector d7 d6 d5 d4 d3 d2 d1 d0 v7 v6 v5 v4 v3 v2 v1 v0

um008101-0601 serial input/output 282 figure 116. write register 2 write register 3 wr3 ( figure 117 ) contains receiver logic control bits and parameters. (table 20) receiver enable (d0) a 1 programmed into this bit allows receive operations to begin. set this bit only after all other receive parameters are set and the receiver is completely initialized. table 20. write register 3 logic control d7 d6 d5 d4 receiver bits/ chars receiver bits/char 0 auto enables enter hunt phase d3 d2 d1 d0 receiver crc enable address search mode sync char load inhibit receiver enable v0 v1 v2 v3 d7 d6 d5 d4 d3 d2 d1 d0 interrupt v4 v5 v6 v7 vector
z80 cpu peripherals user manual um008101-0601 serial input/output 283 sync character load inhibit (d1) sync characters preceding the message (leading sync characters) are not loaded into the receive buffers if this option is selected. because crc calculations are not stopped by sync character stripping, this feature should be enabled only at the beginning of the message. address search mode (d2) if sdlc is selected, no receive interrupts can occur in the address search mode without an address match. therefore, messages containing addresses that do not match the programmed address in wr6 or the global ( 1111 1111 ) are rejected. receiver crc enable (d3) if this bit is set, crc calculation starts or restarts at the beginning of the last character transferred from the receive shift register to the buffer stack. this start or restart occurs regardless of the number of characters in the stack. for more information about setting this bit, see ? sdlc receive crc checking ? (sdlc receive section) and ? crc error checking ? (synchronous receive section). enter hunt phase (d4) the z80 sio automatically enters the hunt phase after a reset. however, it can be re-entered if character synchronization is lost (synchronous mode) or if the contents of an incoming message are not needed (sdlc mode). the hunt phase is reentered by writing a 1 to bit d4. this sets the sync/ hunt bit (d4) in rr0. auto enables(d5) if this mode is selected, dcd and cts become the receiver and transmitter enables, respectively. if this bit is not set, dcd and cts are simply inputs to their corresponding status bits in rr0.

um008101-0601 serial input/output 284 figure 117. write register 3 receiver bits/characters 1 and 0 (d7 and d6) used together, these bits determine the number of serial receive bits assembled to form a character. both bits may be changed during the time that a character is being assembled, but they must be changed before the currently programmed number of bits is reached. write register 4 wr4 contains the control bits that affect both the receiver and transmitter. in the transmit and receive initialization routine, these bits should be set beforeissuingwr1,wr3,wr5,wr6,andwr7. table 21. serial bits/character d7 d6 bits/character 00 5 01 7 10 6 11 8 rx enable sync character load inhibit address search mode (sdlc) rx crc enable d7 d6 d5 d4 d3 d2 d1 d0 enter hunt phase auto enables 00 01 10 11 rx 5 bits/character rx 7 bits/character rx 6 bits/character rx 8 bits/character
z80 cpu peripherals user manual um008101-0601 serial input/output 285 parity (d0) if this bit is set, an additional bit position is added to transmitted data and is expected in receive data. this added bit position is in addition to those bits specified in the bits/character control. in the receive mode, the parity bit received is transferred to the cpu as part of the character, unless eight bits/ character is selected. parity even/odd (d1) if parity is specified, this bit determines whether the bit is sent and checked as even or odd (1 = even). stopbits0and1(d2andd3) these bits determine the number of stop bits added to each asynchronous character sent. the receiver always checks for one stop bit. a special mode (00) designates that a synchronous mode is to be selected. table 22. write register 4 rx and tx control d7 d6 d5 d4 d3 d2 d1 d0 clock rate 1 clock rate 0 sync modes 1 sync modes 0 stop bits 1 stop bits 0 parity even/ odd parity table 23. stop bits d3 stop bits 1 d2 stop bits 0 result 0 0 sync modes 0 1 1 stop bit per character 1 0 1-1/2 stop bits per character 1 1 2 stop bits per character

um008101-0601 serial input/output 286 sync modes 0 and 1 (d4 and d5) these bits select various options for character synchronization. figure 118. write register 4 clockrate0and1(d6andd7) these bits specify the multiplier between the clock (txc and rxc )anddata rates. for synchronous modes, the x1 clock rate must be specified. any rate may be specified for asynchronous modes; however, the same rate must be table 24. sync modes sync mode 1 sync mode 0 result 0 0 8-bit programmed sync 0 1 16-bit programmed sync 1 0 sdlcmode(01111110flagpattern) 1 1 external sync mode parity enable parity even/odd d7 d6 d5 d4 d3 d2 d1 d0 00 01 10 11 sync modes enable 1 stop bit/character 1-1/2 stop bits/character 2 stop bits/character 00 01 10 11 8-bit sync character 16-bit sync character sdlc mode (0111 1110 flag) external sync mode 00 01 10 11 x1 clock mode x16 clock mode x32 clock mode x64 clock mode
z80 cpu peripherals user manual um008101-0601 serial input/output 287 used for both the receiver and transmitter. the system clock in all modes must be set to at least 4.5 times the data rate. if the x1 clock rate is selected, bit synchronization must be performed externally. write register 5 wr5 contains control bits that affect the operation of transmitter, with the exception of d2, which affects the transmitter and receiver. transmit crc enable (d0) this bit determines if crc is calculated on a specific transmit character. if it is set at the time the character is loaded from the transmit buffer into the transmit shift register, crc is calculated on the character. crc is not auto- matically sent unless this bit is set when the transmit underrun condition occurs. table 25. clock rate clock rate 1 clock rate 0 result 0 0 data rate x1 = clock rate 0 1 data rate x16 = clock rate 1 0 data rate x32 = clock rate 1 1 data rate x64 = clock rate table26.writeregister5transmittercontrol d7 d6 d5 d4 d3 d2 d1 do dtr tx bits/ char 1 tx bits/ char 0 send break tx enable crc-16/ sdlc rts tx crc enable

um008101-0601 serial input/output 288 request to send (d1) this is the control bit for the rts pin. when the rts bit is set, the rts pin goes low; when reset, rts goes high. in the asynchronous mode, rts goes high only after all the bits of the character are transmitted and the transmitter buffer is empty. in synchronous modes, the pin directly follows the state of the bit. crc-16/sdlc (d2) this bit selects the crc polynomial used by both the transmitter and receiver. when set, the crc-16 polynomial (x 16 +x 15 +x 2 +1)isused; when reset, the sdlc polynomial (x 16 +x 12 +x 5 +1)isused.ifthesdlc mode is selected, the crc generator and checker are preset to 1s and a special check sequence is used. the sdlc crc polynomial must be selected when the sdlc mode is selected. if the sdlc mode is not selected, the crc generator and checker are preset to 0s for both polynomials. transmit enable (d3) data is not transmitted until this bit is set, and the transmit data output is held marking. data or sync characters in the process of being transmitted are completely sent if this bit is reset after transmission is started. if the transmitter is disabled during the transmission of a crc character, sync, or flag characters are sent instead of crc. send break (d4) when set, this bit immediately forces the transmit data output to the spacing condition, regardless of any data being transmitted. when reset, txd returns to marking.
z80 cpu peripherals user manual um008101-0601 serial input/output 289 figure 119. write register 5 transmit bits/characters 0 and 1 (d5 and d6) together, d6 and d5 control the number of bits in each byte transferred to the transmit buffer. bits to be sent must be right justified, least-significant bits first. the five- or-less mode allows transmission of one to five bits per character; however, the cpu should format the data character as depicted in the following table. table 27. transmit bits d6 transmit bits/ character 1 d5 transmit bits/ character 0 bits/character 0 0 five or less 017 106 118 tx crc enable rts d7 d6 d5 d4 d3 d2 d1 d0 00 01 10 11 8-bit sync character 16-bit sync character sdlc mode (0111 1110 flag) external sync mode sdlc/crc-16 tx enable send break dtr

um008101-0601 serial input/output 290 data terminal ready (d7) this is the control bit for the dtr pin. when set, dtr is active (low); when reset, dtr is inactive (high). write register 6 this register is programmed to contain the transmit sync character in the monosync mode, the first eight bits of a 16-bit sync character in the bisync mode, or a transmit sync character in the external sync mode. in the sdlc mode, it is programmed to contain the secondary address field, which is used to compare against the address field of the sdlc frame. figure 120. write register 6 table 28. data character format d7 d6 d5 d4 d3 d2 d1 d0 result 1 1 1 1 0 0 0 d sends one data bit 111000ddsendstwodatabits 1 1 0 0 0 d d d sendsthreedatabits 1 0 0 0 d d d d sends four data bits 0 0 0 d d d d d sends five data bits sync bit 0 sync bit 1 sync bit 2 sync bit 3 d7 d6 d5 d4 d3 d2 d1 d0 * sync bit 4 sync bit 5 sync bit 6 sync bit 7 *also sdlc address field
z80 cpu peripherals user manual um008101-0601 serial input/output 291 write register 7 this register is programmed to contain the receive sync character in the monosync mode, a second byte (last eight bits) of a 16-bit sync character in the bisync mode, or a flag character (0111 1110) in the sdlc mode. wr7 is not used in the external sync mode. figure 121. write register 7 table29.writeregister6transmitsync d7 d6 d5 d4 d3 d2 d1 d0 sync 7 sync 6 sync 5 sync 4 sync 3 sync 2 sync 1 sync 0 table30.writeregister7receivesync d7 d6 d5 d4 d3 d2 d1 sync 15 sync 14 sync 13 sync 12 sync 11 sync 10 sync 9 sync 8 sync bit 8 sync bit 9 sync bit 10 sync bit 11 d7 d6 d5 d4 d3 d2 d1 d0 * sync bit 12 sync bit 13 sync bit 14 sync bit 15 *for sdlc it must be programmed to ? 0111 1110 ? for flag recognition

um008101-0601 serial input/output 292 read registers the z80 sio contains three registers, rr2-rr0 (figure 122 through figure 124), that are read to obtain the status information for each channel, with the exception of rr2-channel b. the status information includes error conditions, interrupt vector, and standard communications-interface signals. to read the contents of a selected read register other than rrd, the system program must first write the pointer byte to wr0, in exactly the same way as a write register operation. then, by executing an input instruction, the contents of the addressed read register can be read by the cpu. the status bits of rr0 and rr1 are carefully grouped to simplify status monitoring. for example, when the interrupt vector indicates that a special receive condition interrupt occurred, all the appropriate error bits can be read from a single register (rr1). read register 0 this register contains the status of the receive and transmit buffers; the dcd ,cts , and sync inputs; the transmit underrun/eom latch; and the break/abort latch. receive character available (do) this bit is set when at least one character is available in the receive buffer; it is reset when the receive fifo is empty. table 31. read register 0 rx and tx buffers d7d6idsd4d3d2d1d0 break/ abort transmit underrun eom cts sync/ hunt buffer empty dcd transmit pending interrupt pending (ch.a only) receive character available
z80 cpu peripherals user manual um008101-0601 serial input/output 293 interrupt pending (d1) anyinterruptingconditioninthez80siocausesthisbittoset;however,it is readable only in channel a. this bit is primarily used in applications not having vectored interrupts available. during the interrupt service routine in these applications, this bit indicates if any interrupt conditions are present in the z80 sio. this eliminates the need for analyzing all the bits of rr0 in both channels a and b. bit d1 is reset when all the interrupting conditions are satisfied. this bit is always 0 in channel b. transmit buffer empty (d2) this bit is set whenever the transmit buffer becomes empty, except when a crc character is being sent in a synchronous or sdlc mode. the bit is reset when a character is loaded into the transmit buffer. this bit is in the set condition after a reset. data carrier detect (d3) the dcd bit indicates the state of the dcd input at the time of the last change of any of the five external/status bits (dcd ,cts ,sync/hunt, break/ abort, or transmit underrun/eom). any transition of the dcd input causes the dcd bit to latch and causes an external/status interrupt. to read the current state of the dcd bit, this bit must be read immediately following a reset external/status interrupt command. sync/hunt (d4) because this bit is controlled differently in the asynchronous, synchronous, and sdlc modes, its operation is somewhat more complex than that of the other bits and therefore requires more explanation. in asynchronous modes, the operation of this bit is similar to the dcd status bit, except that sync/hunt shows the state of the sync input. any high-to-low transition on the sync pin sets this bit and causes an external/status interrupt (if enabled). the reset external/status interrupt command is issued to clear the interrupt. a low-to-high transition clears

um008101-0601 serial input/output 294 this bit and sets the external/status interrupt. when the external/status interrupt is set by the change in state of any other input or condition, this bit shows the inverted state of the sync pin at the time of the change. this bit must be read immediately following a reset external/status interrupt command to read the current state of tile sync input. figure 122. read register 0 in the external sync mode, the sync/hunt bit operates similar to the asyn- chronous mode, except the enter hunt mode control bit enables the external sync detection logic. when the external sync mode and enter hunt mode bits are set for example, when the receiver is enabled following a reset, the sync input must be held high by the external logic until external character synchronization is achieved. a high at the sync input holds the sync/hunt status bit in the reset condition. when external synchronization is achieved, sync must be driven low on the second rising edge of rxc after that rising edge of rxc on which the last bit of the sync character was received. in other words, after the sync pattern is detected, the external logic must wait for two full receive clock cycles to activate the sync input. when sync is forced low, keep it low until the cpu informs the external sync logic that synchronization is lost or that a new message is about to start. refer to figure 122 for timing details. the high-to-low transition of the sync input sets the sync/hunt bit, which, in turn, sets the external/status interrupt. the cpu must clear the interrupt by issuing the reset external/status interrupt command. rx character available int pending (ch.a only tx buffer empty dcd d7 d6 d5 d4 d3 d2 d1 d0 * sync/hunt tx underrun/eom break/abort *used with ? external/status interrupt mode cts
z80 cpu peripherals user manual um008101-0601 serial input/output 295 when the sync input goes high again, another external/ status interrupt is generated that must also be cleared. the enter hunt mode control bit is set whenever character synchronization is lost or the end of message is detected. in this case, the z80 sio again looks for a high-to-low transition of the sync input and the operation repeats as explained previously. this implies the cpu should also inform the external logic that character synchronization has been lost and that the z80 sio is wailing for sync to become active. in the monosync and bisync receive modes, the sync/hunt status bit is initially set to 1 by the enter hunt mode bit. the sync/hunt bit is reset when the z80 sio establishes character synchronization. the high-to-low transition of the sync/hunt bit causes an external/status interrupt that must be cleared by the cpu issuing the reset external/ status interrupt command. this enables the z80 sio to detect the next transition of other external/status bits. when the cpu detects the end of message or loss of character synchroniza- tion, it sets the enter hunt mode control bit, which-in turn-sets the sync/ hunt bit to 1. the low-to-high transition of the sync/hunt fit sets the external/status interrupt, which must also be cleared by the reset external/ status interrupt command. the sync pin functions as an output in this mode and goes low when a sync pattern is detected in the data stream. in the sdlc mode, the sync/hunt bit is initially set by the enter hunt mode bit, or when the receiver is disabled. it is reset to 0 when the opening flag of the first frame is detected by the z80 sio. the external/status inter- rupt is also generated, and should be handled as discussed previously. unlike the monosync and bisync modes, when the sync/hunt bit is reset in the sdlc mode, it does not need to be set when the end of message is detected. the z80 sio automatically maintains synchronization. the sync/ hunt bit can only be set again by the enter hunt mode bit or by disabling the receiver.

um008101-0601 serial input/output 296 clear to send, (d5). this bit is similar to the dcd bit, except that it shows the inverted state of the cts pin. transmit underrun/end of message (d6) this bit is in a set condition following a reset, either internal or external. the only the reset transmit underrun/eom latch command (wr0, d6 and d7) can reset this bit. when the transmit underrun condition occurs, this bit is set; causing the external/status interrupt, which is reset by issuing the reset external/status interrupt command bits (wr0). this status bit, along with other control bits, has an important function in controlling a transmit operation. for more information, see ? bisync transmit underrun ? and ? sdlc transmit underrun ? . break/abort (d7) in the asynchronous receive mode, this bit is set when a break sequence (null character plus framing error) is detected in the data stream. the external/status interrupt, if enabled, is set when break is detected. the interrupt service routine must issue the reset external/status interrupt command (wr0, cmd2) to the break detection logic, enabling the break sequence termination to be recognized. the break/abort bit is reset when the termination of the break sequence is detected in the incoming data stream. the termination of the break sequence also causes the external/status interrupt to set. the reset external/status interrupt command must be issued to enable the break detection logic to look for the next break sequence. when a single extra- neous null character is present in the receiver after the termination of a break; it should be read and discarded. in the sdlc receive mode, this status bit is set by the detection of an abort sequence (seven or more 1s). the external/status interrupt is handled the same way as a break. the break/abort bit is not used in the synchro- nous receive mode.
z80 cpu peripherals user manual um008101-0601 serial input/output 297 read register 1 this register contains the special receive condition status bits and residue codes for the i-field in the sdlc receive mode. all sent (d0) in asynchronous modes, this bit is set when all the characters have completely cleared the transmitter. transitions of this bit do not cause inter- rupts and it is always set in synchronous modes. residue codes 0, 1, and 2 (d3-d1) in sdlc receive mode, these three bits indicate the length of the i-field, when the i-field is not an integral multiple of the character length. these codes are only meaningful for a transfer in which the end-of-frame bit is set (sdlc). for a receive character length of eight bits per character, the codes signify the following: table 32. read register 1 special receive condition status d7 d6 ds d4 d3 d2 d1 d0 end of frame (sdlc) crc/ framing error receiver overrun error parity error residue code 2 residue code 1 residue code 0 all sent table33.residuecodes residue code 2 residue code 1 residue code 0 i-field bits in previous byte i-field bits in second previous byte 10003 01004 11005 00106 10107

um008101-0601 serial input/output 298 i-field bits are always right justified. if a receive character length is different from eight bits is used for the i- field, a table similar to the previous one may be constructed for each different character length. for no residue, that is, when the last character boundary coincides with the boundary of the i-field and crc field, the residue codes are: 01108 11118 00028 table34.receivecharacterlength bits per character residue code 2 residue code 1 residue code 0 8 bits per character 0 1 1 7 bits per character 0 0 0 6 bits per character 0 1 0 5 bits per character 0 0 1 table33.residuecodes residue code 2 residue code 1 residue code 0 i-field bits in previous byte i-field bits in second previous byte
z80 cpu peripherals user manual um008101-0601 serial input/output 299 figure 123. read register 1 parity error (d4) when parity is enabled, this bit is set for those characters whose parity does not match the programmed sense (even/odd). the bit is latched, so when an error occurs, the bit remains set until given the error reset command (wr0). receive overrun error (d5) this bit indicates that more than three characters have been received without a read from the cpu. only the character that has been written over is flagged with this error, but when this character is read, the error condition is latched until reset by the error reset command. if status affects vector is enabled, the character that has been overrun interrupts with a special receive condition vector. 100 010 110 001 101 011 111 000 parity error rx overrun error crc/framing error end-of-frame (sdlc) d7 d6 d5 d4 d3 d2 d1 d0 *residue data for eight rx bits/character programmed all sent ifieldbits in previous byte 0 0 0 0 0 0 1 2 i field bits in second previous byte 3 4 5 6 7 8 8 8 *

um008101-0601 serial input/output 300 crc/framing error (d6) if a framing error occurs (asynchronous modes), this bit is set (and not latched) for the receive character in which the framing error occurred. detection of a framing error adds an additional one-half bit time to the character time, so the framing error is not interpreted as a new start bit. in synchronous and sdlc modes, this bit indicates the result of comparing the crc checker to the appropriate check value. this bit is reset by issuing an error reset command. the bit is not latched, so it is always updated when the next character is received. when used for crc error and status in synchronous modes, it is usually set because most bit combinations result in a non-zero crc except for a correctly completed message. end-of-frame (d7) this bit is used only with the sdlc mode and indicates that a valid ending flag has been received and that the crc error and residue codes are also valid. this bit can be reset by issuing the error reset command. it is also updated by the first character of the following frame. read register (channel b only) this register contains the interrupt vector written into wr2 if the status affects vector control bit is not set. if the control bit is set, it contains the modified vector listed in the status affects vector paragraph of the write register 1 section. when this register is read, the vector returned is modi- fied by the highest priority interrupting condition at the time of the read. if no interrupts are pending, the vector is modified with v3 = 0, v2 = 1, and v1 = 1. this register is read only through channel b. table 35. interrupt vector d7 d6 d5 d4 d3 d2 d1 d0 v7 v6 v5 v4 v3* v2* v1* v0 *variable if ? status affects vector ? is programmed
z80 cpu peripherals user manual um008101-0601 serial input/output 301 figure 124. read register 2 (channel b only) applications overview flexibility and versatility make the z80 sio useful for numerous applica- tions, a few of which are described here. these examples demonstrate how several applications combine the z80 sio with other members of the z80 family. figure 125 depicts simple processor-to-processor communication over a direct line. both remote processors in this system communicate to the z80 cpu with different protocols and data rates. depending on the complexity of the application, other z80 peripheral circuits (z80 ctc, for example) may be required. the unused z80 sio channel is available to control other peripherals or to connect with remote processors. v0 v1* v2* v3* d7 d6 d5 d4 d3 d2 d1 d0 interrupt v4 v5 v6 v7 vector *variable if ? status affects vector ? is programmed

um008101-0601 serial input/output 302 figure 125. synchronous/asynchronous processor-to-processor communication (direct wire to remote locations) figure 126 illustrates how both channels of a single z80 sio are used with modems that have primary and secondary or reverse channel options. alternatively, two modems without these options can be connected to the z80 sio. a correct baud-rate generator (z80 ctc) must be used for asyn- chronous modems. figure 126. synchronous/asynchronous processor-to-processor communication (using telephone line) figure 127 depicts the z80 sio in a data concentrator, a relatively complex application that uses two z80 sios to perform a variety of func- tions. the data concentrator can be used to collect data from many termi- nals over low-speed lines and transmit it over a single high-speed line after editing and reformatting. z80 cpu z80 sio rsxyz drivers/ receivers rsxyz drivers/ receivers z80 sio z80 cpu rsxyz drivers/ receivers z80 sio z80 cpu z80 cpu z80 sio ch.a ch.b rs driver/ receiver primary channel secondary channel modem (sync or async) data link to remote processor
z80 cpu peripherals user manual um008101-0601 serial input/output 303 the z80 dma controller circuit is used with z80 sio/2 to transmit the reformatted data at high speed with the required protocol. the high-speed modem provides the transmit clock for this channel. the z80 ctc counter- timer circuit supplies the transmit and receive clocks for the low-speed lines and is also used as a time-out counter for various functions. z80 sio/1 controls local or remote terminals. a single intelligent terminal is placed within the dashed lines. the terminal employs a z80 sio to communicate to the data concentrator on one channel while providing the interface to a line printer over its second channel. the intelligent terminal could be designed to operate interactively with the operator. depending on the software and hardware capabilities built into this system, the data concentrator can employ store-and-forward or hold-and-forward methods for regulating information traffic between slow terminals and the high-speed remote processor. if the high-speed channel is provided with a dial-out option, the channel can be connected to a number of remote processors over a switched line.

um008101-0601 serial input/output 304 figure 127. data concentrator keyboard display/ line printer z80 te r m i n a l bus terminal interfaces to r e m o t e high-speed modem system z80 z80 rdy rdy ch.a z80 system bus (data, address, and control) rxca txca z80 cpu and memory intelligent term in al sio clock generator and time out counters terminal interfaces processor memory cpu receivers drivers/ rs 232 receivers drivers/ rs 232 receivers drivers/ rs 232 console sio z80 pio z80 ctc receivers drivers/ rs 232 receivers drivers/ rs 232 sio #2 ch.b dma ch.a z80 sio #1 ch.b communications link (sdlc protocol)
z80 cpu peripherals user manual um008101-0601 serial input/output 305 timing read cycle the timing signals that are generated by a z80 cpu input instruction, which read a data or status byte from the z80 sio, are illustrated in figure 128. figure 128. read cycle timing write cycle figure 129 illustrates the timing and data signals generated by a z80 cpu output instruction, which write a data or control byte to the z80 sio. out channel address t 1 ce iorq rd m1 data t 2 t w t 3 t 1

um008101-0601 serial input/output 306 figure 129. write cycle timing interrupt acknowledge cycle after receiving an interrupt request signal, int pulled low, the z80 cpu sends an interrupt acknowledge signal, m1 and iorq, both low. the daisy-chained interrupt circuits determine the highest priority interrupt requestor. the iei of the highest priority peripheral is terminated high. peripherals that have no interrupt pending or under service are terminated ieo = iei. any peripheral that does have an interrupt pending or under service, forces its ieo low. to insure stable conditions in the daisy-chain, all interrupt status signals are prevented from changing while mi is low. when iorq is low, the highest priority interrupt requestor, which is the one with iei high, places its interrupt vector on the data bus and sets its internal interrupt-underservice latch. see figure 130. channel address t 1 ce iorq rd m1 data t 2 t w t 3 t 1 in
z80 cpu peripherals user manual um008101-0601 serial input/output 307 figure 130. interrupt acknowledge cycle timing return from interrupt cycle normally, the z80 cpu issues a reti, return from interrupt, instruction at the end of an interrupt service routine. the reti is a 2-byte op code, ed-4d, which resets the interrupt-underservice latch that terminates the interrupt just processed. this is accomplished by manipulating the daisy- chaininthefollowingway. the normal daisy-chain operation can detect a pending interrupt; however, it cannot distinguish between an interrupt under service and a pending unacknowledged interrupt of a higher priority. whenever ed is decoded, the daisy-chain is modified by forcing high the ieo of any interrupt not yet acknowledged. thus the daisy-chain identifies the device presently under service as the only one with an iei high and an ieo low. if the next op code byte is 4d, the interrupt-underservice latch is reset. see figure 131. t 1 iorq rd m1 data t 2 t w t 3 t 4 iei vector t w

um008101-0601 serial input/output 308 the tipple time of the interrupt daisy-chain, both the high-to-low and the low-to-high transitions, limits the number of devices that can be placed in the daisy-chain. ripple time can be improved with carry- lookahead, or by extending the interrupt acknowledge cycle. figure 131. return from interrupt cycle timing daisy chain interrupt nesting figure 132 illustrates the daisy-chain configuration of interrupt circuits and their interaction with nested interrupts, which is an interrupt that is inter- rupted by another with a higher priority. each box in the illustration can be a separate external z80 peripheral circuit with a user-defined order of interrupt priorities. however, a similar daisy- chain structure also exists inside the z80 sio, which has six interrupt levels with a fixed order of priorities. the situation illustrated in figure 132 occurs when the transmitter of channel b interrupts and is granted service. while this interrupt is being serviced, it is interrupted by a higher priority interrupt from channel a. the second interrupt is serviced and, upon completion, a reti instruction is t 1 rd m1 t 2 t 3 t 4 iei ieo d7 ? d0 ed 4d t 1 t 2 t 3 t 4 t 1
z80 cpu peripherals user manual um008101-0601 serial input/output 309 executed or a reti command is written to the z80 sio, resetting the interrupt-under-service latch of the channel a interrupt. at this time, the service routine for channel b is resumed. when the service routine is completed, another reti instruction is executed to complete the interrupt service. figure 132. typical interrupt service iei high + high 5. channel b transmitter service routine complete, second reti issued. channel a receiver ieo iei high ieo iei high ieo iei high ieo iei high ieo iei high ieo service completed iei high + high ieo iei high ieo iei high ieo iei high ieo iei high ieo iei high ieo iei high + low ieo iei high ieo iei high ieo iei high ieo iei high ieo iei ieo service resumed low 4. channel a external/status routine complete, reti issued, channel b transmitter service resumed. iei high + low ieo iei high ieo iei high ieo iei high ieo iei high ieo iei ieo service suspended low iei high + low ieo iei high ieo iei high ieo iei high ieo iei high ieo iei ieo under service low channel a transmitter channel a external status channel b receiver channel b transmitter channel b external status 3. external/status channel a interrupts suspending service of channel b transmitter. 2. channel b transmitter interrupts and is acknowledged. 1. priority interrupt daisy chain before any interrupt occurs.

um008101-0601 serial input/output 310

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